UCB1400BE,151 NXP Semiconductors, UCB1400BE,151 Datasheet - Page 6

• Manufacturer Part Number: UCB1400BE,151
• Description: IC AUDIO CODEC 3.3V 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Codec '97r

Specifications of UCB1400BE,151

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 91
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935269304151; UCB1400BE-SNXP; UCB1400BE-SNXP

Philips Semiconductors
8. AC ’97 interface
9397 750 09611
Product data
8.1 Clocking
8.2 Resetting UCB1400
The UCB1400 implements an AC ’97 Revision 2.1 interface. Refer to the Audio
Codec ’97 Component Specification Revision 2.1 from Intel.
The UCB1400 functions only as a primary codec. As such, it derives its clock
internally from an externally attached 24.576 MHz crystal or clock oscillator, and
drives a buffered and divided down (
AC-link under the signal name “BIT_CLK”.
The beginning of all audio sample packets, or Audio Frames, transferred over AC-link
is synchronized to the rising edge of the SYNC signal. SYNC is driven by the AC ’97
Controller. The AC ’97 Controller takes BIT_CLK as an input and generates SYNC by
dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This
yields a 48 kHz SYNC signal whose period defines an audio frame. Data is
transitioned on AC-link on every rising edge of BIT_CLK, and subsequently sampled
on the receiving side of AC-link on each immediately following falling edge of
BIT_CLK.
The UCB1400 recognizes the following types of reset:
After signaling a reset to UCB1400, the AC ’97 Controller should not attempt to play
or capture audio data until it has sampled a “Codec Ready” indication from UCB1400.
•
•
•
Fig 4. UCB1400 and AC ’97 controller connection diagram.
Cold reset: where all UCB1400 logic (registers included) is initialized to its default
state. Initiated by bringing RESET LOW for at least 1 s.
Warm reset: where the contents of the UCB1400 register set are left unaltered.
Initiated by bringing SYNC HIGH for at least 1 s without BIT_CLK.
Register reset: which only initializes the UCB1400 registers to their default states.
Initiated by a write to register 0x00.
Rev. 02 — 21 June 2002
CONTROLLER
AC97
1
2
SDATA_OUT
) clock to its digital companion controller over
SDATA_IN
BIT_CLK
RESET
SYNC
Audio codec with touch screen controller
IRQOUT
and power management monitor
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
UCB1400
SN00237
UCB1400
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