ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 28

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-7:
EUDAST
EUDAND
ESTAT
EIR
ECON1
ETXST
ETXLEN
ERXST
ERXTAIL
ERXHEAD
EDMAST
EDMALEN
EDMADST
EDMACS
ETXSTAT
ETXWIRE
EHT1
EHT2
ETH3
ETH4
EPMM1
EPMM2
EPMM3
EPMM4
EPMCS
ERXFCON
EPMO
MACON1
MACON2
MABBIPG
MAIPG
MACLCON
MAMXFL
Legend:
Name
File
16-Bit
8-Bit
— = unimplemented, read as ‘0’; q = unique MAC address or silicon revision nibble; r = reserved bit, do not modify; x = Reset value unknown. Reset values are shown in hexadecimal for each byte.
MODEXST HASHEN
MAC Maximum Frame Length, High Byte (MAMXFL<15:8>)
CRYPTEN MODEXIF
DMA Checksum, High Byte (EDMACS<15:8>)
Transmit Byte Count on Wire (including collision bytes), High Byte (ETXWIRE<15:8>)
Hash Table Filter (EHT1<15:8>)
Hash Table Filter (EHT2<31:24>)
Hash Table Filter (EHT3<47:40>)
Hash Table Filter (EHT4<63:56>)
Pattern Match Filter Mask (EPMM1<15:8>)
Pattern Match Filter Mask (EPMM2<15:8>)
Pattern Match Filter Mask (EPMM3<15:8>)
Pattern Match Filter Mask (EPMM4<15:8>)
Pattern Match Filter Checksum, High Byte (EPMCS<15:8>)
Pattern Match Filter Offset, High Byte (EPMO<15:8>)
Bit 15
HTEN
Bit 7
INT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
r
ENC424J600/624J600 REGISTER FILE SUMMARY
User-Defined Area Start Pointer (EUDAST<14:8>)
User-Defined Area End Pointer (EUDAND<14:8>)
TX Start Address (ETXST<14:8>)
TX Length (ETXLEN<14:8>)
RX Buffer Start Address (ERXST<14:8>)
RX Tail Pointer (ERXTAIL<14:8>)
RX Head Pointer (ERXHEAD<14:8>)
DMA Start Address (EDMAST<14:8>)
DMA Length (EDMALEN<14:8>)
DMA Destination Address (EDMADST<14:8>)
FCIDLE
DEFER
MPEN
Bit 14
Bit 6
—
—
—
r
r
RXBUSY
HASHOP
HASHIF
Bit 13
BPEN
Bit 5
—
—
—
—
r
r
High Byte (‘H’ Register)
HASHLST
NOBKOFF
CLKRDY
NOTPM
AESIF
Bit 12
Bit 4
—
—
r
r
r
PMEN3
AESST
LINKIF
Bit 11
Bit 3
—
—
r
r
r
r
r
LATECOL MAXCOL EXDEFER
PHYDPX
AESOP1
PMEN2
Bit 10
Bit 2
—
—
r
r
r
r
AESOP0
PMEN1
Bit 1
Bit 9
—
r
r
r
r
r
r
PHYLNK PKTCNT7 PKTCNT6 PKTCNT5 PKTCNT4 PKTCNT3
PKTDEC
PMEN0
Bit 0
Bit 8
—
r
r
r
r
r
MAC Maximum Frame Length, Low Byte (MAMXFL<7:0>)
TX Length (ETXLEN<7:0>)
RX Tail Pointer (ERXTAIL<7:0>)
Transmit Byte Count on Wire (including collision bytes), Low Byte (ETXWIRE<7:0>)
PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN
User-Defined Area Start Pointer (EUDAST<7:0>)
User-Defined Area End Pointer (EUDAND<7:0>)
TX Start Address (ETXST<7:0>)
RX Buffer Start Address (ERXST<7:0>)
RX Head Pointer (ERXHEAD<7:0>)
DMA Start Address (EDMAST<7:0>)
DMA Length (EDMALEN<7:0>)
DMA Destination Address (EDMADST<7:0>)
DMA Checksum, Low Byte (EDMACS<7:0>)
Hash Table Filter (EHT1<7:0>)
Hash Table Filter (EHT2<23:16>)
Hash Table Filter (EHT3<39:32>)
Hash Table Filter (EHT4<55:48>)
Pattern Match Filter Mask (EPMM1<7:0>)
Pattern Match Filter Mask (EPMM2<7:0>)
Pattern Match Filter Mask (EPMM3<7:0>)
Pattern Match Filter Mask (EPMM4<7:0>)
Pattern Match Filter Checksum, Low Byte (EPMCS<7:0>)
CRCEEN
Pattern Match Filter Offset, Low Byte (EPMO<7:0>)
FCOP1
DEFER
Bit 7
Bit 7
—
—
—
—
r
CRCEN
BBIPG6
FCOP0
PKTIF
IPG6
Bit 6
Bit 6
—
—
r
RUNTEEN RUNTEN
BBIPG5
DMAST
DMAIF
IPG5
Bit 5
Bit 5
—
—
r
Low Byte (‘L’ Register)
DMACPY DMACSSD DMANOCS
CRCBAD COLCNT3 COLCNT2 COLCNT1 COLCNT0 00, 00
LOOPBK
BBIPG4
IPG4
Bit 4
Bit 4
—
r
MAXRET3 MAXRET2 MAXRET1 MAXRET0 37, 0F
BBIPG3
UCEN
IPG3
Bit 3
Bit 3
TXIF
r
NOTMEEN
PKTCNT2 PKTCNT1 PKTCNT0 00, 00
HFRMEN
TXABTIF
RXPAUS
BBIPG2
IPG2
Bit 2
Bit 2
PASSALL
RXABTIF
BBIPG1
TXRTS
MCEN
IPG1
Bit 1
Bit 1
r
PCFULIF 0A, 00
FULDPX 40, B2
BBIPG0
RXEN
BCEN
IPG0
Bit 0
Bit 0
r
00, 00
5F, FF
00, 00
00, 00
00, 00
53, 40
5F, FE
53, 40
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 00
00, 59
00, 00
x0, 0D
00, 12
0C, 12
05, EE
Reset