ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 75

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.0
ENC424J600/624J600 differentiates between five
types of Resets:
• Power-on Reset (POR)
• System Reset
• Transmit Only Reset
• Receive Only Reset
• PHY Subsystem Reset
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 7-1.
7.1
Power-on Reset occurs when V
This allows the device to start in the initialized state
when V
operate correctly. The POR circuitry is always enabled.
To ensure proper POR operation, the application circuit
must meet the specified minimum rise rate of V
(SV
After a Power-on Reset, the contents of the SRAM buffer
and cryptographic memories are unknown. However, all
registers will be loaded with their specified Reset values.
The PHY and other logic should still not be accessed
immediately after the POR. See Section 8.1 “Reset”
for the recommended Reset procedure.
FIGURE 7-1:
 2010 Microchip Technology Inc.
DD
, DC parameter D003).
DD
RESET
Power-on Reset
is adequate for the device’s digital logic to
Transmit Reset
Receive Reset
System Reset
PHY Reset
(ETHRST)
(RXRST)
(TXRST)
(PRST)
ON-CHIP RESET CIRCUIT
POR
DD
rises above V
POR
DD
.
ENC424J600/624J600
7.2
A System Reset reverts all registers back to their
default
COCON<3:0> (ECON2<11:8>), which controls the
frequency output on CLKOUT. All transmit, receive,
MAC, PHY, DMA and cryptographic logic are reset.
Additionally, if the SPI interface is used, the current
internal bank selection is reset to Bank 0. The packet
buffer, cryptographic memories and the PSP address
latch used in Multiplexed Parallel modes are unaffected
by a System Reset.
To initiate a System Reset, set the ETHRST bit
(ECON2<4>). The bit is automatically cleared by
hardware. After setting ETHRST, a delay of 25  s is
required before the ENCX24J600 can be accessed
again through the SPI or PSP interfaces. Additionally,
all PHY registers and status bits derived from the PHY
should not be accessed or used for an additional period
of 256  s.
A System Reset does not cause the SPISEL and
PSPCFGx pin states to be relatched. Therefore, the cur-
rently selected controller interface remains available
after issuing a System Reset and waiting the required
25  s.
System Reset
Reset
values,
Reset I/O Interface
and CLKOUT
Reset SFRs and
SPI Bank Select
Reset TX
Reset RX
Reset PHY
with
the
DS39935C-page 73
exception
of