ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 41

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
ENC424J600/624J600 devices implement an optional
SPI I/O port for applications where a parallel micro-
controller interface is not available or is undesirable. An
SPI port is commonly available on many micro-
controllers, and can be simulated in software on regular
I/O pins where it is not implemented. This makes the
SPI port ideal for using ENC424J600/624J600 devices
with the widest possible range of host controllers.
4.1
The SPI port on ENC424J600/624J600 devices
operates as a slave port only. The host controller must
be configured as an SPI master that generates the
Serial Clock (SCK) signal.
This implementation supports SPI Mode 0,0, which
requires:
• SCK is Idle at a logic low state
• Data is clocked in on rising clock edges and
Other SPI modes that use inverted clock polarity and/or
phase are not supported.
Commands and data are sent to the device on the SI
pin. Data is driven out on the SO line on the falling edge
of SCK. The CS pin must be held low while any
operation is performed, and returned to logic high when
finished.
When CS is in the inactive (logic high) state, the SO pin
is set to a high-impedance state and becomes 5V toler-
ant. This allows the ENCX24J600 to be connected to a
single SPI bus shared by multiple SPI slave devices
that also go to a high-impedance state when inactive.
For details on the physical connections to the interface,
see Section 2.7 “Host Interface Pins”.
 2010 Microchip Technology Inc.
changes on falling clock edges
SERIAL PERIPHERAL
INTERFACE (SPI)
Physical Implementation
ENC424J600/624J600
4.2
The SPI interface supports a unique instruction set,
consisting of 47 distinct opcodes. These include a large
number of optimized opcodes that perform a wide
range of frequently performed operations with a mini-
mum of SPI protocol overhead. Complete Ethernet
functionality can be achieved with as few as six N-byte
opcodes. The use of the other 41 is optional; however,
doing so will generally improve overall system
performance.
The SPI opcodes are divided into four families:
• Single Byte: Direct opcode instructions; designed
• Two-Byte: Direct opcode instruction; designed for
• Three-Byte: Opcode with word length argument;
• N-Byte: Opcode with one or more bytes of
A complete summary of all opcodes is provided in
Table 4-1. A detailed explanation of each opcode family
follows.
for task-oriented SFR operations with no data
returned
SFR operation with byte data returned
includes read and write operations, designed for
pointer manipulation with word length data
returned
argument; includes read and write operations
designed for general memory space access with
one or more bytes of data returned
SPI Instruction Set
DS39935C-page 39