ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 81

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 8-2:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-12,
bit 11-8
bit 7-5
bit 4-0
Note 1:
LACFG3
DEVID2
R/W-0
R-0
These configurations require that a bi-color LED be connected between the LEDA and LEDB pins, and
that LACFG<3:0> and LBCFG<3:0> be set to the same value. See Section 2.5.1 “Using Bi-Color
LEDs” for detailed information.
LACFG<3:0>: LEDA Configuration bits and
LBCFG<3:0: LEDB Configuration bits
1111 = Display link and speed state, transmit and receive events
1110 = Display link and duplex state, transmit and receive events
1101 = Reserved
1100 = Display link state, collision events; pin is driven high when a link is present and driven low
1011 = Display link state, transmit and receive events; pin is driven high when a link is present and
1010 = Display link state, receive events; pin is driven high when a link is present and driven low while
1001 = Display link state, transmit events; pin is driven high when a link is present and driven low while
1000 = Display speed state; pin is driven high when in 100 Mbps mode and a link is present
0111 = Display duplex state; pin is driven high when the PHY is in full duplex (PHYDPX (ESTAT<10>)
0110 = Display transmit and receive events; pin is driven high while a packet is either being received
0101 = Display receive events; pin is driven high while a packet is being received
0100 = Display transmit events; pin is driven high while a packet is being transmitted
0011 = Display collision events; pin is temporarily driven high when a collision occurs
0010 = Display link state; pin is driven high when linked
0001 = On (pin is driven high)
0000 = Off (pin is driven low)
DEVID<2:0>: Device ID bits
001 = ENC624J600 family device
REVID<4:0>: Silicon Revision ID bits
Indicates current silicon revision.
LACFG2
DEVID1
R/W-0
R-0
EIDLED: ETHERNET ID STATUS/LED CONTROL REGISTER
temporarily when a collision occurs
driven low while a packet is being received or transmitted
a packet is being received
a packet is being transmitted
is ‘ 1 ’) and a link is present
or transmitted
W = Writable bit
‘1’ = Bit is set
LACFG1
DEVID0
R/W-1
R-1
LACFG0
REVID4
R/W-0
R
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ENC424J600/624J600
LBCFG3
REVID3
R/W-0
R
LBCFG2
REVID2
R/W-1
R
(1)
(1)
x = Bit is unknown
LBCFG1
REVID1
R/W-1
R
DS39935C-page 79
LBCFG0
REVID0
R/W-0
R
bit 8
bit 0