LAN9115-MT SMSC, LAN9115-MT Datasheet - Page 120

• Manufacturer Part Number: LAN9115-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9115-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1010

Revision 1.5 (07-11-08)
6.1.2
RX Status FIFO
TX Status FIFO
RX_DP_CTRL
RX Data FIFO
READING...
RX_DROP
AFTER
Special Restrictions on Back-to-Back Read Cycles
There are also restrictions on specific back-to-back read operations. These restrictions concern
reading specific registers after reading resources that have side effects. In many cases there is a delay
between reading the LAN9115, and the subsequent indication of the expected change in the control
register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have
been established. These periods are specified in
processor is required to wait the specified period of time between read operations of specific
combinations of resources. The wait period is dependant upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum wait time restriction is met.
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on
the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number of reads
may be reduced as long as the total time is equal to, or greater than the time specified in the table.
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
Note 6.1
This restriction is only applicable after a fast-forward operation has been completed and
the RX_FFWD bit has been cleared. Refer to
Forward," on page 58
WAIT FOR THIS MANY
NS…
165
165
330
Table 6.2 Read After Read Timing Rules
165
330
for more information.
DATASHEET
Table 6.2
120
OR PERFORM THIS MANY
READS OF BYTE_TEST…
(ASSUMING TCYC OF
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Table 6.2, "Read After Read Timing
also shows the number of dummy reads that are
165NS)
1
1
1
2
2
Section 3.14.1.1, "Receive Data FIFO Fast
BEFORE READING...
RX Status FIFO
TX Status FIFO
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
RX_DROP
Note 6.1
Rules". The host
SMSC LAN9115
Datasheet