LAN9115-MT SMSC, LAN9115-MT Datasheet - Page 124

• Manufacturer Part Number: LAN9115-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9115-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1010

Revision 1.5 (07-11-08)
6.5
SYMBOL
t
t
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
t
t
t
t
t
t
csdv
acyc
t
asu
adv
don
doff
doh
csh
ah
In this mode the upper address inputs are not decoded, and any burst read of the LAN9115 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9115. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines. In this mode, performance is improved by allowing an unlimited number of back-to-back
DWORD or WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip
Select (nCS) or Read Enable (nRD). When either or both of these control signals go high, they must
remain high for the period specified.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Note: The “Data Bus” width is 16 bits
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
RX Data FIFO Direct PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
DATASHEET
124
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
165
13
0
0
0
0
TYP
MAX
30
40
7
SMSC LAN9115
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns