LAN9115-MT SMSC, LAN9115-MT Datasheet - Page 59

IC ETHERNET CTRLR 10/100 100TQFP

LAN9115-MT

Manufacturer Part Number
LAN9115-MT
Description
IC ETHERNET CTRLR 10/100 100TQFP
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet

Specifications of LAN9115-MT

Controller Type
Ethernet Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
IEEE 802.3 or IEEE 802.3u
Data Rate
10 Mbps or 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
1.8 V
Maximum Operating Temperature
+ 70 C
Ethernet Connection Type
100BASE-TX or 10BASE-T
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1010

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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
3.14.3
29:16
BITS
31
30
15
14
13
12
Reserved. This bit is reserved. Reads 0.
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
filtering.
Packet Length. The size, in bytes, of the corresponding received frame.
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the
Internal logical “or” of bits 11,7,6 and 1.
Reserved. These bits are reserved. Reads 0.
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
Length Error (LE). When set, this bit indicates that the actual length does not match with the
length/type field of the received frame.
Note 3.17 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are
RX Status Format
32-bits wide.
transactions.
Host Read
Order
Last
2nd
1st
Figure 3.19
Figure 3.19 RX Packet Format
31
ofs + First Data DWORD
DATASHEET
Optional offset DWORD0
Optional offset DWORDn
Optional Pad DWORD0
Optional Pad DWORDn
Last Data DWORD
describes the host read ordering for pairs of atomic 16-bit
DESCRIPTION
59
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Revision 1.5 (07-11-08)

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