LAN9115-MT SMSC, LAN9115-MT Datasheet - Page 15

• Manufacturer Part Number: LAN9115-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9115-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1010

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
53,56-59,62-
SPEED_SEL
43-46,49-
PIN NO.
12-18
64
92
93
94
72
76
0
1
Host Address
Read Strobe
Write Strobe
FIFO Select
Chip Select
Host Data
Interrupt
Request
NAME
100MBPS
10MBPS
SPEED
FIFO_SEL
SYMBOL
Table 2.1 Host Bus Interface Signals
Table 2.2 Default Ethernet Settings
D[15:0]
A[7:1]
nWR
nRD
nCS
IRQ
DATASHEET
DEFAULT ETHERNET SETTINGS
HALF-DUPLEX
HALF-DUPLEX
BUFFER
O8/OD8
DUPLEX
TYPE
I/O8
15
IS
IS
IS
IS
IS
PINS
16
#
7
1
1
1
1
1
Bi-directional data port.
7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
Active low strobe to indicate a read
cycle.
Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9115
when it is in a reduced power state.
Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9115 when it is in a
reduced power state.
Programmable Interrupt request.
Programmable polarity, source and
buffer types.
When driven high all accesses to the
LAN9115 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
DESCRIPTION
AUTO NEG.
DISABLED
ENABLED
Revision 1.5 (07-11-08)