ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 26
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ENC28J60-I/SS
Manufacturer Part Number
ENC28J60-I/SS
Description
IC ETHERNET CTRLR W/SPI 28SSOP
Manufacturer
Microchip Technology
Datasheet
1.ENC28J60SS.pdf
(98 pages)
Specifications of ENC28J60-I/SS
Package / Case
28-SSOP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
2.25 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current (max)
180 mA
Package
28SSOP
Standard Supported
IEEE 802.3
Communication Mode
Full Duplex|Half Duplex
Network Interface
MII|MIIM
Data Rate
10 Mbps
Host Interface
SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC28J60-I/SS
Manufacturer:
MURATA
Quantity:
30 000
ENC28J60
REGISTER 3-6:
DS39662C-page 24
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8-6
bit 5
bit 4-0
Note 1:
U-0
U-0
—
—
Reset values of the Duplex mode/status bit depends on the connection of the LED to the LEDB pin (see
Section 2.6 “LED Configuration” for additional details).
Unimplemented: Read as ‘0’
TXSTAT: PHY Transmit Status bit
1 = PHY is transmitting data
0 = PHY is not transmitting data
RXSTAT: PHY Receive Status bit
1 = PHY is receiving data
0 = PHY is not receiving data
COLSTAT: PHY Collision Status bit
1 = A collision is occuring
0 = A collision is not occuring
LSTAT: PHY Link Status bit (non-latching)
1 = Link is up
0 = Link is down
DPXSTAT: PHY Duplex Status bit
1 = PHY is configured for full-duplex operation (PHCON1<8> is set)
0 = PHY is configured for half-duplex operation (PHCON1<8> is clear)
Unimplemented: Read as ‘0’
PLRITY: Polarity Status bit
1 = The polarity of the signal on TPIN+/TPIN- is reversed
0 = The polarity of the signal on TPIN+/TPIN- is correct
Unimplemented: Read as ‘0’
U-0
U-0
—
—
PHSTAT2: PHYSICAL LAYER STATUS REGISTER 2
W = Writable bit
‘1’ = Bit is set
TXSTAT
PLRITY
R-0
R-0
RXSTAT
(1)
R-0
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COLSTAT
R-0
U-0
—
LSTAT
R-0
U-0
—
© 2008 Microchip Technology Inc.
x = Bit is unknown
DPXSTAT
U-0
R-x
—
(1)
U-0
U-0
—
—
bit 8
bit 0