ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 41
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ENC28J60-I/SS
Manufacturer Part Number
ENC28J60-I/SS
Description
IC ETHERNET CTRLR W/SPI 28SSOP
Manufacturer
Microchip Technology
Datasheet
1.ENC28J60SS.pdf
(98 pages)
Specifications of ENC28J60-I/SS
Package / Case
28-SSOP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
2.25 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current (max)
180 mA
Package
28SSOP
Standard Supported
IEEE 802.3
Communication Mode
Full Duplex|Half Duplex
Network Interface
MII|MIIM
Data Rate
10 Mbps
Host Interface
SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC28J60-I/SS
Manufacturer:
MURATA
Quantity:
30 000
7.0
7.1
The MAC inside the ENC28J60 will automatically gener-
ate the preamble and Start-Of-Frame delimiter fields
when transmitting. Additionally, the MAC can generate
any padding (if needed) and the CRC if configured to do
so. The host controller must generate and write all other
frame fields into the buffer memory for transmission.
FIGURE 7-1:
© 2008 Microchip Technology Inc.
bit 7-4
bit 3
bit 2
bit 1
bit 0
TRANSMITTING AND
RECEIVING PACKETS
Transmitting Packets
Unused
PHUGEEN: Per Packet Huge Frame Enable bit
When POVERRIDE = 1:
1 = The packet will be transmitted in whole
0 = The MAC will transmit up to the number of bytes specified by MAMXFL. If the packet is larger
When POVERRIDE = 0:
This bit is ignored.
PPADEN: Per Packet Padding Enable bit
When POVERRIDE = 1:
1 = The packet will be zero padded to 60 bytes if it is less than 60 bytes
0 = The packet will be transmitted without adding any padding bytes
When POVERRIDE = 0:
This bit is ignored.
PCRCEN: Per Packet CRC Enable bit
When POVERRIDE = 1:
1 = A valid CRC will be calculated and attached to the frame
0 = No CRC will be appended. The last 4 bytes of the frame will be checked for validity as a
When POVERRIDE = 0:
This bit is ignored.
POVERRIDE: Per Packet Override bit
1 = The values of PCRCEN, PPADEN and PHUGEEN will override the configuration defined by
0 = The values in MACON3 will be used to determine how the packet will be transmitted
bit 7
—
than MAMXFL, it will be aborted after MAMXFL is reached.
CRC.
MACON3
FORMAT FOR PER PACKET CONTROL BYTES
—
—
—
Preliminary
PHUGEEN
Additionally, the ENC28J60 requires a single per packet
control byte to precede the packet for transmission. The
per packet control byte is organized as shown in
Figure 7-1. Before transmitting packets, the MAC
registers which alter the transmission characteristics
should be initialized as documented in Section 6.0
“Initialization”.
For an example of how the entire transmit packet and
results will look in memory, see Figure 7-2.
PPADEN
PCRCEN
ENC28J60
POVERRIDE
DS39662C-page 39
bit 0