ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 31

• Manufacturer Part Number: ENC28J60-I/SS
• Description: IC ETHERNET CTRLR W/SPI 28SSOP
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SS

• Package / Case: 28-SSOP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 2.25 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current (max): 180 mA
• Package: 28SSOP
• Standard Supported: IEEE 802.3
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII|MIIM
• Data Rate: 10 Mbps
• Host Interface: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2.4
The Write Buffer Memory (WBM) command allows the
host controller to write bytes to the integrated 8-Kbyte
transmit and receive buffer memory.
If the AUTOINC bit in the ECON2 register is set, after
the last bit of each byte is written, the EWRPT Pointer
will automatically be incremented to point to the next
sequential address (current address + 1). If address,
1FFFh, is written with AUTOINC set, the Write Pointer
will increment to 0000h.
The WBM command is started by lowering the CS pin.
The WBM opcode should then be sent to the
ENC28J60, followed by the 5-bit constant, 1Ah. After
the WBM command and constant are sent, the data to
be stored in the memory pointed to by EWRPT should
be shifted out MSb first to the ENC28J60. After 8 data
bits are received, the Write Pointer will automatically
increment if AUTOINC is set. The host controller can
continue to provide clocks on the SCK pin and send
data on the SI pin, without raising CS, to keep writing to
the memory. In this manner, with AUTOINC enabled, it
is possible to continuously write sequential bytes to the
buffer memory without any extra SPI command
overhead.
The WBM command is terminated by bringing up the
CS pin. Refer to Figure 4-6 for a detailed illustration of
the write sequence.
4.2.5
The Bit Field Set (BFS) command is used to set up to
8 bits in any of the ETH Control registers. Note that this
command cannot be used on the MAC registers, MII
registers, PHY registers or buffer memory. The BFS com-
mand uses the provided data byte to perform a bit-wise
OR operation on the addressed register contents.
FIGURE 4-6:
© 2008 Microchip Technology Inc.
SCK
CS
SO
SI
0
0
BIT FIELD SET COMMAND
WRITE BUFFER MEMORY
COMMAND
Opcode
1
1
1
2
WRITE BUFFER MEMORY COMMAND SEQUENCE
1
3
1
4
Address
0
5
1
6
0
7
7
8
High-Impedance State
6
9
Preliminary
10 11 12 13 14 15 16 17 18 19 20 21 22
5
Data Byte 0
4
3
2
The BFS command is started by pulling the CS pin low.
The BFS opcode is then sent, followed by a 5-bit
address (A4 through A0). The 5-bit address identifies
any of the ETH registers in the current bank. After the
BFS command and address are sent, the data byte
containing the bit field set information should be sent,
MSb first. The supplied data will be logically ORed to
the content of the addressed register on the rising
edge of the SCK line for the D0 bit.
If the CS line is brought high before eight bits are
loaded, the operation will be aborted for that data
byte. The BFS operation is terminated by raising the
CS pin.
4.2.6
The Bit Field Clear (BFC) command is used to clear up
to 8 bits in any of the ETH Control registers. Note that
this command cannot be used on the MAC registers,
MII registers, PHY registers or buffer memory. The BFC
command uses the provided data byte to perform a bit-
wise NOTAND operation on the addressed register
contents. As an example, if a register had the contents
of F1h and the BFC command was executed with an
operand of 17h, then the register would be changed to
have the contents of E0h.
The BFC command is started by lowering the CS pin.
The BFC opcode should then be sent, followed by a
5-bit address (A4 through A0). The 5-bit address
identifies any of the ETH registers in the current bank.
After the BFC command and address are sent, a data
byte containing the bit field clear information should
be sent, MSb first. The supplied data will be logically
inverted and subsequently ANDed to the contents of
the addressed register on the rising edge of the SCK
line for the D0 bit.
The BFC operation is terminated by bringing the CS pin
high. If CS is brought high before eight bits are loaded,
the operation will be aborted for that data byte.
1 D0
7
BIT FIELD CLEAR COMMAND
6
5
Data Byte 1
4
ENC28J60
3
2
1
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