ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 42
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ENC28J60-I/SS
Manufacturer Part Number
ENC28J60-I/SS
Description
IC ETHERNET CTRLR W/SPI 28SSOP
Manufacturer
Microchip Technology
Datasheet
1.ENC28J60SS.pdf
(98 pages)
Specifications of ENC28J60-I/SS
Package / Case
28-SSOP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
2.25 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current (max)
180 mA
Package
28SSOP
Standard Supported
IEEE 802.3
Communication Mode
Full Duplex|Half Duplex
Network Interface
MII|MIIM
Data Rate
10 Mbps
Host Interface
SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC28J60-I/SS
Manufacturer:
MURATA
Quantity:
30 000
ENC28J60
FIGURE 7-2:
To achieve the example layout shown in Figure 7-2 and
to transmit a packet, the host controller should:
1.
2.
3.
4.
5.
If a DMA operation was in progress while the TXRTS bit
was set, the ENC28J60 will wait until the DMA opera-
tion is complete before attempting to transmit the
packet. This possible delay is required because the
DS39662C-page 40
Appropriately program the ETXST Pointer to
point to an unused location in memory. It will
point to the per packet control byte. In the
example, it would be programmed to 0120h. It is
recommended that an even address be used for
ETXST.
Use the WBM SPI command to write the per
packet control byte, the destination address, the
source MAC address, the type/length and the
data payload.
Appropriately program the ETXND Pointer. It
should point to the last byte in the data payload.
In the example, it would be programmed to
0156h.
Clear EIR.TXIF, set EIE.TXIE and set EIE.INTIE
to enable an interrupt when done (if desired).
Start the transmission process by setting
ECON1.TXRTS.
Buffer Pointers
ETXST = 0120h
ETXND = 0156h
SAMPLE TRANSMIT PACKET LAYOUT
Address
016Ch
016Dh
016Ah
016Bh
016Eh
0120h
0121h
0122h
0156h
0157h
0158h
0159h
tsv[23:16]
tsv[31:24]
tsv[39:32]
tsv[47:40]
tsv[55:48]
Memory
tsv[15:8]
data[m]
tsv[7:0]
data[1]
data[2]
0Eh
Preliminary
Status Vector
Data Packet
DMA and transmission engine share the same memory
access port. Similarly, if the DMAST bit in ECON1 is set
after TXRTS is already set, the DMA will wait until the
TXRTS bit becomes clear before doing anything. While
the transmission is in progress, none of the unshaded
bits (except for the EECON1 register’s bits) in Table 7-2
should be changed. Additionally, none of the bytes to be
transmitted should be read or written to through the SPI.
If the host controller wishes to cancel the transmission,
it can clear the TXRTS bit.
When the packet is finished transmitting or is aborted
due to an error/cancellation, the ECON1.TXRTS bit will
be cleared, a seven-byte transmit status vector will be
written to the location pointed to by ETXND + 1, the
EIR.TXIF will be set and an interrupt will be generated
(if enabled). The ETXST and ETXND Pointers will not
be modified. To check if the packet was successfully
transmitted, the ESTAT.TXABRT bit should be read. If
it was set, the host controller may interrogate the
ESTAT.LATECOL bit in addition to the various fields in
the transmit status vector to determine the cause. The
transmit status vector is organized as shown in
Table 7-1. Multi-byte fields are written in little-endian
format.
Control
Description
PHUGEEN, PPADN,
PCRCEN and POVERRIDE
Destination Address,
Source Address,
Type/Length and Data
Status Vector
Written by the Hardware
Start of the Next Packet
© 2008 Microchip Technology Inc.