LAN91C96-MU SMSC, LAN91C96-MU Datasheet - Page 36

• Manufacturer Part Number: LAN91C96-MU
• Description: IC ETHERNET CTLR MAC PHY 100TQFP
• Manufacturer: SMSC

Specifications of LAN91C96-MU

• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1018

5.6
Revision 1.0 (10-24-08)
PCMCIA Configuration Registers
Address 8000-8003h
The PCMCIA Configuration Registers are stored inside the LAN91C96 above the external Attribute
Memory address space. These registers are used to configure and control the PCMCIA related
functionality of the Ethernet. These registers are eight bit wide and reside on even locations. The
LAN91C96 will ignore odd access to this area and ignore writes. The device will read zero’s on odd
access. This address offset has changed from prior LAN9XXX PCMCIA Family designs to allow a larger
address range for other attribute memory data. This data could be a larger card information structure or a
XIP data image.
Attribute Memory map
The EPROM attribute memory decodes are shown below. Internal to the LAN91C96, the memory
addressing logic will allow byte or word access on even byte boundaries. LAN91C96 uses address A0-9,
A15, along with nREG, nCE1, nWE and nOE. An on odd byte address access (A0=1), the LAN91C96 will
generate a arbitrary value of Zero (0) since the PCMCIA specification states that the high byte of a word
access in attribute memory is a don’t care. This allows backward compatibility to 8 bit hosts.
With or Without 64x16 bit Serial EEPROM:
PCMCIA CONFIGURATION REGISTERS DESCRIPTION
Ethernet Function (Base Address 8000h)
8000h - Ethernet Configuration Option Register (ECOR)
BIT 7 - SRESET: This bit when set will clear all internal registers associated with the Ethernet function
except itself and it will also lower the nIREQ/READY pin. When this bit is cleared, nIREQ/READY pin will
be raised.
BIT 6 - LevIREQ: This bit is read only and reads as a one to indicate level mode interrupts are used.
Pulse mode interrupts are not supported.
BIT 5, 4, 3 - Not defined
BIT 2 - WRATTRIB: This bit when set (1) allows writing into the external attribute memory space.
BIT 1 - Not Defined
BIT 0 - Enable Function: This bit enables (1) or disables (0) the Ethernet function. While the Ethernet
function is disabled it remains in power down mode, no access to the Ethernet I/O space (i.e. The bank
SRESET
7
0
ATTRIBUTE MEMORY
LevIREQ
(Read
8000h - 8003h
only)
ADDRESS
6
1
0 - 7FFEh
5
0
DATASHEET
EXTERNAL EPROM
4
0
Page 36
STORE
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
X
3
0
0
ATTRIB
WR
2
0
CONFIGURATIO
N REGISTERS
X
1
0
Function
Enable
SMSC LAN91C96 5v&3v
0
0
Datasheet