LAN91C96-MU SMSC, LAN91C96-MU Datasheet - Page 56

• Manufacturer Part Number: LAN91C96-MU
• Description: IC ETHERNET CTLR MAC PHY 100TQFP
• Manufacturer: SMSC

Specifications of LAN91C96-MU

• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1018

Note:
Note:
Revision 1.0 (10-24-08)
For software compatibility with future versions, the value read from each FIFO register is intended to be written
into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).
FAILED
REMPTY
TEMPTY
I/O SPACE - BANK2
FAILED - A ”0” indicates a successful allocation completion. If the allocation fails the bit is set and only
cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For
polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is
synchronized to the read operation. Sequence:
1.
2.
3.
ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request.
The value is only valid if the FAILED bit is clear.
For software compatibility with future versions, the value read from the ARR after an allocation request is
intended to be written into the PNR as is, without masking higher bits (provided FAILED = “0”).
I/O SPACE - BANK2
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO.
The packet numbers to be processed by the interrupt service routines are read from this register.
REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the
Interrupt Status Register.
TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid
if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 6) or 8).
TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the
Interrupt Status Register.
TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if
TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.
OFFSET
OFFSET
1
1
1
Allocate Command
Poll ALLOC_INT bit until set
Read Allocation Result Register
3
4
0
0
0
ALLOCATION RESULT REGISTER
FIFO PORTS REGISTER
0
0
0
DATASHEET
NAME
NAME
0
0
0
Page 56
ALLOCATED PACKET NUMBER
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
RX FIFO PACKET NUMBER
TX FIFO PACKET NUMBER
0
0
0
READ ONLY
READ ONLY
0
0
0
TYPE
TYPE
0
0
0
SYMBOL
SYMBOL
SMSC LAN91C96 5v&3v
FIFO
ARR
0
0
0
Datasheet