LAN91C96-MU SMSC, LAN91C96-MU Datasheet - Page 67

• Manufacturer Part Number: LAN91C96-MU
• Description: IC ETHERNET CTLR MAC PHY 100TQFP
• Manufacturer: SMSC

Specifications of LAN91C96-MU

• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1018

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
8.1
SMSC LAN91C96 5v&3v
1 ISSUE ALLOCATE MEMORY FOR TX - N
2 WAIT FOR SUCCESSFUL COMPLETION
3 LOAD TRANSMIT DATA - Copy the TX packet
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
5
6
BYTES - the MMU attempts to allocate N bytes
of RAM.
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
Typical Flow of Events for Transmit (Auto Release = 0)
S/W DRIVER
DATASHEET
Page 67
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
a)
b)
Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO
into the TX completion FIFO. Interrupt is
generated by the TX completion FIFO being
not empty.
If a TX failure occurs on any packets, TX
INT is generated and TXENA is cleared,
transmission sequence stops. The packet
number of the failure packet is presented at
the TX FIFO PORTS Register.
MAC SIDE
Revision 1.0 (10-24-08)