DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 102

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bits 8 to 10/Receive Done-Queue Status-Bit Threshold Setting (RDQT0 to RDQT2). These bits determine
when the DMA sets the receive DMA done-queue write (RDQW) status bit in the status register for DMA
(SDMA) register.
9.2.5 DMA Channel Configuration RAM
There is a set of 768 dwords (3 dwords per channel times 256 channels) on-board the device that the host
uses to configure the DMA. It uses the DMA to store values locally when it is processing a packet. Most
of the fields within the DMA configuration RAM are for DMA use and the host never writes to these
fields. The host is only allowed to write (configure) to the lower word of dword 2 for each HDLC
channel. The host-configurable fields are denoted with a thick box as shown below.
Figure 9-9. Receive DMA Configuration RAM
HDLC
Channel 256
HDLC
Channel 1
HDLC
Channel 2
000 = set the RDQW status bit after each descriptor write to the done queue
001 = set the RDQW status bit after 2 or more descriptors are written to the done queue
010 = set the RDQW status bit after 4 or more descriptors are written to the done queue
011 = set the RDQW status bit after 8 or more descriptors are written to the done queue
100 = set the RDQW status bit after 16 or more descriptors are written to the done queue
101 = set the RDQW status bit after 32 or more descriptors are written to the done queue
110 = set the RDQW status bit after 64 or more descriptors are written to the done queue
111 = set the RDQW status bit after 128 or more descriptors are written to the done queue
014h
000h
004h
008h
00Ch
010h
BF4h
BF8h
BFCh
msb
31
Threshold
Count (3)
Threshold
Count (3)
Threshold
Count (3)
Start Descriptor Pointer (16)
Start Descriptor Pointer (16)
Start Descriptor Pointer (16)
Byte Count (13)
Byte Count (13)
Byte Count (13)
Current Packet Data Buffer Address (32)
Current Packet Data Buffer Address (32)
Current Packet Data Buffer Address (32)
Receive DMA Configuration RAM
102 of 183
FBF
FBF
FBF
unused (5)
unused (5)
unused (5)
Fields shown within the thick box
are written by the Host; all other
fields are for usage by the DMA and
can only be read by the Host
Current Descriptor Pointer (16)
Current Descriptor Pointer (16)
Current Descriptor Pointer (16)
Threshold(3)
Threshold(3
Threshold(3
Unused (4)
Unused (4)
Unused (4)
Size
(2)
Size
(2)
Size
(2)
CH
EN
CH
EN
CH
EN
lsb
0