DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 38
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DS31256
Manufacturer Part Number
DS31256
Description
IC CTRLR HDLC 256-CHANNEL 256BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS31256.pdf
(183 pages)
Specifications of DS31256
Controller Type
HDLC Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
500mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS31256
Manufacturer:
DALLAS
Quantity:
20 000
Bit #
Name
Default
Bit #
Name
Default
Bit 14/Status Bit for Local Bus Error (LBE). This status bit applies to the local bus when it is operated in PCI
bridge mode. It is set to 1 when the local bus LRDY signal is not detected within nine LCLK periods. This
indicates to the host that an aborted local bus access has occurred. If enabled through the LBE bit in the interrupt
mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the PINTA signal pin
and also at the LINT if the local bus is in configuration mode. The LBE bit is meaningless when the local bus is
operated in the configuration mode and should be ignored.
Bit 15/Status Bit for Local Bus Interrupt (LBINT). This status bit is set to 1 if the local bus LINT signal has
been detected as asserted. This status bit is only valid when the local bus is operated in PCI bridge mode. The
LBINT bit is cleared when read and is not set again until the LINT signal pin once again has been detected as
asserted. If enabled through the LBINT bit in the interrupt mask for SM (ISM), the setting of this bit causes a
hardware interrupt at the PCI bus through the PINTA signal pin. The LBINT bit is meaningless when the local bus
is operated in the configuration mode and should be ignored.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Status Bit for Receive Change-of-Frame Alignment (SRCOFA)
Bit 1/Status Bit for Transmit Change-of-Frame Alignment (STCOFA)
Bit 2/Status Bit for Change of State in BERT (SBERT)
Bit 3/Status Bit for PCI System Error (PSERR)
Bit 4/Status Bit for PCI System Error (PPERR)
Bit 14/Status Bit for Local Bus Error (LBE)
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
LBINT
n/a
15
7
0
0
ISM
Interrupt Mask Register for SM
0024h
LBE
n/a
14
6
0
0
n/a
n/a
13
5
0
0
PPERR
n/a
12
38 of 183
4
0
0
PSERR
n/a
11
3
0
0
SBERT
n/a
10
2
0
0
STCOFA
n/a
1
0
9
0
SRCOFA
n/a
0
8
0
0