DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 56
![IC CTRLR HDLC 256-CHANNEL 256BGA](/photos/6/82/68222/406-256-bga_sml.jpg)
DS31256
Manufacturer Part Number
DS31256
Description
IC CTRLR HDLC 256-CHANNEL 256BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS31256.pdf
(183 pages)
Specifications of DS31256
Controller Type
HDLC Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
500mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS31256
Manufacturer:
DALLAS
Quantity:
20 000
Bit 14/Route Data from BERT (TBERT). Setting this bit routes DS0 data to the TD pin from the BERT block
instead of from the HDLC controller. If the DS0 channel has been configured for 56kbps operation (T56 = 1), the
LSB of each DS0 channel is not routed from the BERT block but instead is forced to 1. In order for the data to
make it from the BERT block, the host must also configure the BERT for the proper port through the master
control register (Section 5). This bit overrides TFAO and TCHEN.
Bit 15/Transmit DS0 Channel Enable (TCHEN). This bit must be set for each active DS0 channel in a
channelized application. In a channelized application, although a DS0 channel is deactivated, the channel can still
be set up to route data from the BERT block. In addition, although a DS0 channel is active, the loopback function
(CNLB = 1) overrides this activation and routes receive data to the TD pin instead of from the HDLC. In an
unchannelized mode (TUEN = 1), only the TCHEN bit in T[n]CFG0 needs to be configured.
6.4 Receive V.54 Detector
Each port within the device contains a V.54 loop pattern detector. V.54 is a pseudorandom pattern that is
sent for at least 2 seconds, followed immediately by an all-ones pattern for at least 2 seconds if the
channel is to be placed into loopback. The exact pattern and sequence is defined in Annex B of ANSI
T1.403-1995.
When a port is configured for unchannelized operation (RUEN = 1), all data entering the port through
RD is routed to the V.54 detector. If the host wishes not to use the V.54 detector, the SLBP status bits in
the status V.54 (SV54) register should be ignored, and their corresponding interrupt mask bits in ISV54
should be set to 0 to keep from disturbing the host. Details about the status and interrupt bits can be
found in Section 5.
When the port is configured for channelized operation (RUEN = 0), it is the host’s responsibility to
determine which DS0 channels should be searched for the V.54 pattern. In channelized applications, it
may be that there are multiple HDLC channels the host wishes to look in for the V.54 pattern. If this is
true, then the host performs the routine shown in
Figure
6-5.
0 = do not route data from BERT
1 = route data from BERT (override the data from the HDLC controller)
0 = deactivated DS0 channel
1 = active DS0 channel
56 of 183
Table
6-B. A flow chart of the same routine is shown in