DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 166

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

well as all test registers remain at their previous states. A rising edge on JTCLK with JTMS high moves
the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low keeps the controller in the
Shift-IR state while moving data one stage through the instruction shift register.
Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is
high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning
process.
Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on
JTCLK puts the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is
low during a rising edge on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS high puts the controller in the Update-IR state. The
controller loops back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.
Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on
the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the
current instruction. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state.
With JTMS high, the controller enters the Select-DR-Scan state.
12.3 Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output, and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI
and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage
toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with
JTMS high moves the controller to the Update-IR state. The falling edge of that same JTCLK latches the
data in the instruction shift register to the instruction parallel output.
supported by the DS31256 and their respective operational binary codes.
Table 12-A. Instruction Codes
SAMPLE/PRELOAD. SAMPLE/PRELOAD is a mandatory instruction for the IEEE 1149.1
specification that supports two functions. The digital I/Os of the DS31256 can be sampled at the
boundary scan register without interfering with the normal operation of the device by using the Capture-
DR state. SAMPLE/PRELOAD also allows the DS31256 to shift data into the boundary scan register
through JTDI using the Shift-DR state.
EXTEST. EXTEST allows testing of all interconnections to the DS31256. When the EXTEST
instruction is latched in the instruction register, the following actions occur. Once enabled through the
Update-IR state, the parallel outputs of all digital output pins are driven. The boundary scan register is
connected between JTDI and JTDO. The Capture-DR samples all digital inputs into the boundary scan
register.
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
INSTRUCTION
SELECTED REGISTER
Device Identification
Boundary Scan
Boundary Scan
Bypass
Bypass
Bypass
166 of 183
INSTRUCTION CODES
010
111
000
011
100
001
Table 12-A
shows instructions