DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 69

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Bit #
Name
Default
Bit #
Name
Default
7.2 HDLC Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)
Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive HDLC
definition RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the
channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready
to be read from the RHCD register, the IAB bit is set to 0. When the host wishes to write data to the internal
receive HDLC definition RAM, the host should write this bit to 0. This causes the device to take the data that is
currently present in the RHCD register and write it to the channel location indicated by the HCID bits. When the
device completes the write, the IAB is set to 0.
Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit sets to 1 until the data is ready to be read. It is set to 0 when the data is ready
to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write
operation completes.
Register Name:
Register Description:
Register Address:
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Receive Transparent Enable (RTRANS). When this bit is set low, the HDLC controller performs flag
delineation, zero destuffing, abort detection, octet length checking (if enabled through ROLD), and FCS checking
(if enabled through RCRC0/1). When this bit is set high, the HDLC controller does not perform flag delineation,
00000000 (00h) = HDLC channel number 1 (also used for the fast HDLC engine on port 0)
00000001 (01h) = HDLC channel number 2 (also used for the fast HDLC engine on port 1)
00000010 (02h) = HDLC channel number 3 (also used for the fast HDLC engine on port 2)
00000011 (03h) = HDLC channel number 4
11111111 (FFh) = HDLC channel number 256
RABTD
HCID7
IAB
n/a
15
15
7
0
0
7
0
0
RHCDIS
Receive HDLC Channel Definition Indirect Select
0400h
RHCD
Receive HDLC Channel Definition
0404h
HCID6
RCS
IARW
n/a
14
6
0
0
14
6
0
0
HCID5
RBF
n/a
13
5
0
0
n/a
13
5
0
0
HCID4
RID
n/a
12
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4
0
0
n/a
12
4
0
0
RCRC1
HCID3
n/a
11
3
0
0
n/a
11
3
0
0
RCRC0
HCID2
n/a
10
2
0
0
n/a
10
2
0
0
ROLD
HCID1
n/a
1
0
9
0
n/a
1
0
9
0
RTRANS
RZDD
HCID0
n/a
0
0
8
0
0
0
8
0