DS21FT42 Maxim Integrated Products, DS21FT42 Datasheet - Page 36

• Manufacturer Part Number: DS21FT42
• Description: IC FRAMER T1 4X3 12CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FT42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 225mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FRAMER LOOPBACK
When CCR1.0 is set to a one, the DS21Q42 will enter a Framer LoopBack (FLB) mode. This loopback
is useful in testing and debugging applications. In FLB, the DS21Q42 will loop data from the transmit
side back to the receive side. When FLB is enabled, the following will occur:
1. An unframed all one’s code will be transmitted at TPOS and TNEG
2. Data at RPOS and RNEG will be ignored
3. All receive side signals will take on timing synchronous with TCLK instead of RCLK
Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will
cause an unstable condition.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB)
TFM
SYMBOL
RSLC96
TSLC96
RB8ZS
TB8ZS
TZSE
TFM
RFM
TB8ZS
POSITION
CCR2.7
CCR2.6
CCR2.5
CCR2.4
CCR2.3
CCR2.2
CCR2.1
TSLC96
NAME AND DESCRIPTION
Transmit Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
Transmit B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this
bit to a one in D4 framing applications. Must be set to one to
source the Fs pattern. See Section 19 for details.
0 = SLC–96/Fs–bit insertion disabled
1 = SLC–96/Fs–bit insertion enabled
Transmit FDL Zero Stuffer Enable. Set this bit to zero if
using the internal HDLC/BOC controller instead of the
legacy support for the FDL. See Section 19 for details.
0 = zero stuffer disabled
1 = zero stuffer enabled
Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
Receive B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
Receive SLC–96 Enable. Only set this bit to a one in
D4/SLC–96 framing applications. See Section 19 for details.
0 = SLC–96 disabled
1 = SLC–96 enabled
TZSE
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RFM
RB8ZS
RSLC96
(LSB)
RZSE