DS21FT42 Maxim Integrated Products, DS21FT42 Datasheet - Page 61

• Manufacturer Part Number: DS21FT42
• Description: IC FRAMER T1 4X3 12CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FT42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 225mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively.
RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a USART or LAPD controller in
Fractional T1 or ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section
24 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS
(Address=6C to 6E Hex)
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address=32 to 34 Hex)
16.
Each framer in the DS21Q42 contains dual two–frame (386 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps) which is the E1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the T1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544 MHz or
2.048 MHz). The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full
controlled slip capability which is necessary for this second purpose. Both elastic stores within the
framer are fully independent and no restrictions apply to the sourcing of the various clocks that are
applied to them. The transmit side elastic store can be enabled whether the receive elastic store is
(MSB)
(MSB)
CH16
CH24
CH16
CH24
CH8
CH8
SYMBOL
SYMBOL
CH1 - 24
CH1 - 24
CLOCK BLOCKING REGISTERS
ELASTIC STORES OPERATION
CH15
CH23
CH15
CH23
CH7
CH7
RCBR1.0 - 3.7
TCBR1.0 - 3.7
CH14
CH22
CH14
CH22
POSITION
POSITION
CH6
CH6
CH13
CH21
CH13
CH21
CH5
CH5
NAME AND DESCRIPTION
NAME AND DESCRIPTION
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel
time
1 = force the RCHBLK pin high during this channel time
Transmit Channel Blocking Control Bits.
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
CH12
CH20
CH12
CH20
CH4
CH4
61 of 114
CH11
CH19
CH19
CH3
CH11
CH3
CH10
CH18
CH2
CH10
CH18
CH2
(LSB)
CH17
(LSB)
CH1
CH9
CH17
CH1
CH9
TCBR1 (32)
TCBR2 (33)
TCBR3 (34)
RCBR2 (6D)
RCBR1 (6C)
RCBR3 (6E)
The