DS21FT42 Maxim Integrated Products, DS21FT42 Datasheet - Page 84

• Manufacturer Part Number: DS21FT42
• Description: IC FRAMER T1 4X3 12CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FT42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 225mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The JTAG feature is only available when the DS21Q42 feature set is selected (FMS = 0). The JTAG
feature is disabled when the DS21Q42 is configured for emulation of the DS21Q41B (FMS = 1). FMS is
tied to ground for the DS21FF42/DS21FT42.Details on Boundary Scan Architecture and the Test Access
Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST*, JTCLK, JTMS, JTDI, and JTDO. See
the pin descriptions for details.
BOUNDARY SCAN ARCHITECTURE Figure 22-1
23.2 TAP CONTROLLER STATE MACHINE
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine.
Please see Figure 23.2 for details on each of the states described below.
Tap Controller
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK.
Test-Logic-Reset
Upon power up of the DS21Q42, the TAP Controller will be in the Test-Logic-Reset state. The
Instruction register will contain the IDCODE instruction. All system logic of the DS21Q42 will operate
normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and
Test registers will remain idle.
Select-DR-Scan
10K
+V
JTDI
10K
+V
JTMS
Test Access Port
Boundary Scan
Identification
Instruction
Bypass
Register
Register
Register
Controller
Register
JTCLK
10K
+V
JTRST
Select
Output Enable
MUX
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JTDO