DP83902AVLJ National Semiconductor, DP83902AVLJ Datasheet - Page 45
DP83902AVLJ
Manufacturer Part Number
DP83902AVLJ
Description
IC CTRLR SER NETWORK IN 100PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83902AVJGNOPB.pdf
(70 pages)
Specifications of DP83902AVLJ
Controller Type
Serial Network Interface Controller
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
140mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP83902AVLJ
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13 0 Bus Arbitration and Timing
The FIFO at the Beginning of Transmit
Before transmitting the ST-NIC performs a prefetch from
memory to load the FIFO The number of bytes prefetched
Maximum Bus Latency for Byte Mode
TL F 11157– 60
Transmit Prefetch Timing
(Continued)
45
is the programmed FIFO threshold The next BREQ is not
issued until after the ST-NIC actually begins transmitting
data i e after SFD The Transmit Prefetch diagram illus-
trates this process
Maximum Bus Latency for Word Mode
TL F 11157 – 59
TL F 11157 – 61