DP83902AVLJ National Semiconductor, DP83902AVLJ Datasheet - Page 49
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DP83902AVLJ
Manufacturer Part Number
DP83902AVLJ
Description
IC CTRLR SER NETWORK IN 100PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83902AVJGNOPB.pdf
(70 pages)
Specifications of DP83902AVLJ
Controller Type
Serial Network Interface Controller
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
140mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP83902AVLJ
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Manufacturer
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13 0 Bus Arbitration and Timing
SLAVE MODE TIMING
When CS is low the ST-NIC becomes a bus slave The CPU
can then read or write any internal registers All register
accesses are byte wide The timing for register access is
shown below The host CPU accesses internal registers
with four address lines RA0–RA3 SRD and SWR strobes
TIME BETWEEN CHIP SELECTS
The ST-NIC requires that successive chip selects be no
closer than 4 bus clocks (BSCK) together If the condition is
violated the ST-NIC may glitch ACK CPUs that operate
from pipelined instructions (i e 386) or have a cache (i e
Time between Chip Selects
Read from Register
(Continued)
Write to Register
49
ADS0 is used to latch the address when interfacing to a
multiplexed address data bus Since the ST-NIC may be a
local bus master when the host CPU attempts to read or
write to the controller an ACK line is used to hold off the
CPU until the ST-NIC leaves master mode Some number of
BSCK cycles is also required to allow the ST-NIC to syn-
chronize to the read or write cycles
486) can execute consecutive I O cycles very quickly The
solution is to delay the execution of consecutive I O cycles
by either breaking the pipeline or forcing the CPU to access
outside its cache
TL F 11157– 63
TL F 11157 – 31
TL F 11157 – 32