AD5930YRUZ Analog Devices Inc, AD5930YRUZ Datasheet - Page 17

• Manufacturer Part Number: AD5930YRUZ
• Description: IC GEN PROG FREQ BURST 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5930YRUZ

• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 24 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Synthesizer Type: Frequency
• Frequency: 25MHz
• Supply Voltage Range: 2.3V To 5.5V
• Supply Current: 2.4mA
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Pin Count: 20
• Screening Level: Automotive
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

This is beneficial for applications where the user needs to burst
a frequency for a set period, and then “listen” for a response
before increasing to the next frequency. Note also that the
beginning of each frequency increment is at midscale (Phase 0
Rad). Therefore, the phase of the signal is always known.
To set up the AD5930 in burst mode, the CW/BURST bit (D7)
in the control register must be set to 1. See the Activating and
Controlling the Sweep section for more details about the burst
output mode.
SERIAL INTERFACE
The AD5930 has a standard 3-wire serial interface, which is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK. The timing diagram for
this operation is given in Figure 4.
The FSYNC input is a level-triggered input that acts as a frame
synchronization and chip enable. Data can only be transferred
into the device when FSYNC is low. To start the serial data
transfer, FSYNC should be taken low, observing the minimum
FSYNC to SCLK falling edge setup time, t
low, serial data is shifted into the device's input shift register on
the falling edges of SCLK for 16 clock pulses. FSYNC can be
taken high after the 16
minimum SCLK falling edge to FSYNC rising edge time, t
Alternatively, FSYNC can be kept low for a multiple of 16 SCLK
pulses, and then brought high at the end of the data transfer. In
this way, a continuous stream of 16-bit words can be loaded while
FSYNC is held low. FSYNC should only go high after the 16th
SCLK falling edge of the last word is loaded.
The SCLK can be continuous, or, alternatively, the SCLK can
idle high or low between write operations.
POWERING UP THE AD5930
When the AD5930 is powered up, the part is in an undefined
state, and therefore, must be reset before use. The eight registers
(control and frequency) contain invalid data and need to be set
to a known value by the user. The control register should be the
first register to be programmed, as this sets up the part. Note
that a write to the control register automatically resets the
internal state machines and provides an analog output of
midscale as it provides the same function as the INTERRUPT
pin. Typically, this is followed by a serial loading of all the
required sweep parameters. The DAC output remains at
midscale until a sweep is started using the CTRL pin.
th
falling edge of SCLK, observing the
7
. After FSYNC goes
8.
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PROGRAMMING THE AD5930
The AD5930 is designed to provide automatic frequency sweeps
when the CTRL pin is triggered. The automatic sweep is
controlled by a set of registers, the addresses of which are given
in Table 5. The function of each register is described in more
detail in the following section.
Table 5. Register Addresses
D15
0
0
0
0
0
1
1
1
1
1
The Control Register
The AD5930 contains a 12-bit control register (see Table 6) that
sets up the operating modes of the AD5930. The different
functions and the various output options from the AD5930 are
controlled by this register.
Table 7 describes the individual bits of the control register.
To address the control register, D15 to D12 of the 16-bit serial
word must be set to 0.
Table 6. Control Register
D15
0
Register Address
D14
0
0
0
0
1
0
1
1
1
1
D14
0
D13
0
0
1
1
0
0
1
1
D13
0
D12
0
1
0
1
0
1
0
1
D12
0
Mnemonic
C
N
∆f
∆f
t
T
F
F
INT
BURST
START
START
REG
INCR
D11 to D0
Control Bits
Name
Control bits
Number of
increments
Lower 12 bits of delta
frequency
Higher 12 bits of
delta frequency
Increment interval
Burst interval
Lower 12 bits of start
frequency
Higher 12 bits of start
frequency
Reserved
Reserved
AD5930