AD5930YRUZ Analog Devices Inc, AD5930YRUZ Datasheet - Page 9

• Manufacturer Part Number: AD5930YRUZ
• Description: IC GEN PROG FREQ BURST 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5930YRUZ

• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 24 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Synthesizer Type: Frequency
• Frequency: 25MHz
• Supply Voltage Range: 2.3V To 5.5V
• Supply Current: 2.4mA
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Pin Count: 20
• Screening Level: Automotive
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Mnemonic
FSADJUST
REF
COMP
AVDD
DVDD
CAP/2.5V
DGND
MCLK
SYNCOUT
MSBOUT
DGND O/P
INTERRUPT
CTRL
SDATA
SCLK
FSYNC
STANDBY
Description
Full-Scale Adjust Control. A resistor (RSET) must be connected externally between this pin and AGND.
This determines the magnitude of the full-scale DAC current. The relationship between R
full-scale current is:
IOUT
where V
Voltage Reference. This pin can be an input or an output. The AD5930 has an internal 1.18 V reference, which
is made available at this pin. Alternatively, this reference can be overdriven by an external reference, with a
voltage range as given in the Specifications section. A 10 nF decoupling capacitor should be connected
between REF and AGND.
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage to AVDD.
Positive Power Supply for the Analog Section. AVDD can have a value from +2.3 V to +5.5 V. A 0.1 µF decoupling
capacitor should be connected between AVDD and AGND.
Positive Power Supply for the Digital Section. DVDD can have a value from +2.3 V to +5.5 V. A 0.1 µF decoupling
capacitor should be connected between DVDD and DGND.
Digital Circuitry. Operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board
regulator. The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5V
to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5V can be shorted to DVDD.
Ground for all Digital Circuitry. This excludes digital output buffers.
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.
The output frequency accuracy and phase noise are determined by this clock.
Digital Output for Sweep Status Information. User selectable for end of sweep (EOS) or frequency increments
through the control register (SYNCOP bit). This pin must be enabled by setting Control Register Bit SYNCOPEN to 1.
Digital Output. The inverted MSB of the DAC data is available at this pin. This output pin must be enabled by
setting bit MSBOUTEN in the control register to 1.
Separate DGND Connection for Digital Output Buffers. Connect to DGND.
Digital Input. This pins acts as an interrupt during a frequency sweep. A low to high transition is sampled by the
internal MCLK, which resets internal state machines. This results in the DAC output going to midscale.
Digital Input. Triple function pin for initialization, start, and external frequency increments. A low-to-high transition,
sampled by the internal MCLK, is used to initialize and start internal state machines, which then execute the pre-
programmed frequency sweep sequence. When in auto-increment mode, a single pulse executes the entire sweep
sequence. When in external increment mode, each frequency increment is triggered by low-to-high transitions.
Serial Data Input. The 16-bit serial data-word is applied to this input with the register address first followed by the
MSB to LSB of the data.
Serial Clock Input. Data is clocked into the AD5930 on each falling SCLK edge.
Active Low Control Input. This is the frame synchronization signal for the serial data. When FSYNC is taken low,
the internal logic is informed that a new word is being loaded into the device.
Active High Digital Input. When this pin is high, the internal MCLK is disabled, and the reference DAC and regulator
are powered down. For optimum power saving, it is recommended to reset the AD5930 before putting it into
standby, as this results in a shutdown current of typically 20 µA.
FULL-SCALE
REFOUT
= 18 × V
= 1.20 V nominal and R
REFOUT
FSADJUST
/R
SYNCOUT
CAP/2.5V
MSBOUT
SET
COMP
DGND
DVDD
MCLK
AVDD
REF
Figure 8. Pin Configuration
10
1
2
3
4
5
6
7
8
9
SET
Rev. 0 | Page 9 of 28
(Not to Scale)
= 6.8 kΩ typical.
TOP VIEW
AD5930
20
19
18
17
16
15
14
13
12
11
IOUTB
IOUT
AGND
STANDBY
FSYNC
SCLK
SDATA
CTRL
INTERRUPT
DGND O/P
SET
and the
AD5930