AD5930YRUZ Analog Devices Inc, AD5930YRUZ Datasheet - Page 19

• Manufacturer Part Number: AD5930YRUZ
• Description: IC GEN PROG FREQ BURST 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5930YRUZ

• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 24 b
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Synthesizer Type: Frequency
• Frequency: 25MHz
• Supply Voltage Range: 2.3V To 5.5V
• Supply Current: 2.4mA
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: TSSOP
• No. Of Pins: 20
• Pin Count: 20
• Screening Level: Automotive
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SETTING UP THE FREQUENCY SWEEP
As stated previously in The Frequency Profile section, the
AD5930 requires certain registers to be programmed to enable a
frequency sweep. The following sections discuss these registers
in more detail.
Start Frequency (F
To start a frequency sweep, the user needs to tell the AD5930
what frequency to start sweeping from. This frequency is stored
in a 24-bit register called F
entire contents of the F
must be preformed, one to the LSBs and the other to the MSBs.
Note that for an entire write to this register, the Control Bit B24
(D11) should be set to 1 with the LSBs programmed first.
In some applications, the user does not need to alter all 24 bits
of the F
the 24-bit register operates as two 12-bit registers, one
containing the 12 MSBs and the other containing the 12 LSBs.
This means that the 12 MSBs of the F
independently of the 12 LSBs, and vice versa. The addresses of
both the LSBs and the MSBs of this register is given in Table 8.
Table 8. F
D15
1
1
Frequency Increments (∆f)
The value in the Δf register sets the increment frequency for the
sweep and is added incrementally to the current output frequency.
Note that the increment frequency can be positive or negative,
thereby giving an increasing or decreasing frequency sweep.
At the start of a sweep, the frequency contained in the F
register is output. Next, the frequency (F
This is followed by (F
Δf value by the number of increments (N
the start frequency (F
sweep. Mathematically this final frequency/stop frequency is
represented by
The Δf register is a 23-bit register, and requires two 16-bit
writes to be programmed. Table 9 gives the addresses associated
with both the MSB and LSB registers of the Δf word.
Table 9. ∆f Register Bits
D15
0
0
0
F
START
D14
0
0
0
START
D14
1
1
START
+ (N
register. By setting the Control Bit B24 (D11) to 0,
D13
1
1
1
Register Bits
INCR
D13
0
0
× Δf).
START
START
START
D12
0
1
1
START
)
), gives the final frequency in the
+ Δf + Δf) and so on. Multiplying the
START
D12
0
1
register, two consecutive writes
D11
12 LSBs of ∆f
<11…0>
0
1
. If the user wishes to alter the
D11 to D0
12 LSBs of F
12 MSBs of F
D10 to D0
11 MSBs of
Δf <22…12>
11 MSBs of
Δf <22…12>
START
START
INCR
word can be altered
), and adding it to
+ Δf ) is output.
START
START
Sweep
Direction
N/A
Positive Δf
(F
Negative ∆f
(F
<11…0>
<23…12>
START
START
START
+ Δf )
− Δf )
Rev. 0 | Page 19 of 28
Number of Increments (N
An end frequency, or a maximum/minimum frequency before
the sweep changes direction is not required on the AD5930.
Instead, this end frequency is calculated by multiplying the
frequency increment value (Δf) by the number of frequency
steps (N
frequency (F
is a 12-bit register, with the address shown in Table 10.
Table 10. N
D15
0
The number of increments is programmed in binary fashion,
with 000000000010 representing the minimum number of
frequency increments (2 increments), and 111111111111
representing the maximum number of increments (4095).
Table 11. N
D11
0000
0000
0000
…
1111
1111
Increment Interval (t
The increment interval dictates the duration of the DAC output
signal for each individual frequency of the frequency sweep.
The AD5930 offers the user two choices:
•
•
This is selected by Bit D13 in the t
Table 12. t
D15
0
0
Programming of this register is in binary form with the
minimum number being decimal 2. Note in Table 12 that 11
bits, Bit D10 to Bit D0, of the register are available to program
the time interval. As an example, if MCLK = 50 MHz, then each
clock period/base interval is (1/50 MHz) = 20 ns. If each
frequency needs to be output for 100 ns, then <00000000101>
or decimal 5 needs to be programmed to this register. Note that
the AD5930 can output each frequency for a maximum
duration of 211 −1 (or 2047) times the increment interval.
The duration is a multiple of cycles of the output frequency.
The duration is a multiple of MCLK periods.
D14
1
1
0000
0000
0000
…
1111
1111
INCR
D14
0
INT
), and adding it to/subtracting it from the start
INCR
INCR
START
Register Bits
D13
0
1
D0
0010
0011
0100
…
1110
1111
Register Bits
Data Bits
), that is, F
D13
0
D12
x
x
Number of Increments
2 frequency increments. This is the
minimum number of frequency
increments.
3 frequency increments.
4 frequency increments.
…
4094 frequency increments.
4095 frequency increments.
INT
)
D12
1
START
INCR
D11
x
x
)
INT
+ N
D11 to D0
12 bits of N
register as shown in Table 12.
D10 to D0
11 bits <10…0>
Fixed number of output
waveform cycles.
11 bits <10…0>
Fixed number of clock
periods.
INCR
× Δ f. The N
INCR
<11…0>
AD5930
INCR
register