AD9958BCPZ Analog Devices Inc, AD9958BCPZ Datasheet - Page 13

• Manufacturer Part Number: AD9958BCPZ
• Description: IC DDS DUAL 500MSPS DAC 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9958BCPZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186)
• Resolution (bits): 10 b
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Pll Type: Frequency Synthesis
• Frequency: 500MHz
• Supply Current: 105mA
• Supply Voltage Range: 1.71V To 1.89V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 56
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9958/PCBZ - BOARD EVALUATION FOR AD9958
• Lead Free Status / Rohs Status: Compliant

75.1 MHz, 100.3 MHz; f
Figure 16. Residual Phase Noise (SSB) with f
Figure 17. Residual Phase Noise (SSB) with f
Figure 18. Residual Phase Noise (SSB) with f
75.1 MHz,100.3 MHz; f
75.1 MHz, 100.3 MHz; f
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
–70
–80
–90
–70
–80
–90
10
10
10
75.1MHz
40.1MHz
100
100
100
40.1MHz
40.1MHz
100.3MHz
15.1MHz
CLK
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
CLK
FREQUENCY OFFSET (Hz)
CLK
15.1MHz
= 500 MHz with REFCLK Multiplier Bypassed
1k
1k
15.1MHz
1k
= 500 MHz with REFCLK Multiplier = 20×
= 500 MHz with REFCLK Multiplier = 5×
100.3MHz
75.1MHz
10k
10k
10k
75.1MHz
100.3MHz
100k
100k
OUT
OUT
OUT
100k
= 15.1 MHz, 40.1MHz,
= 15.1 MHz, 40.1MHz,
= 15.1 MHz, 40.1MHz,
1M
1M
1M
10M
10M
10M
Rev. A | Page 13 of 44
Figure 19. Channel Isolation at 500 MSPS Operation; Conditions are Channel
Figure 20. Power Dissipation vs. Reference Clock Frequency vs. Channel(s)
of Interest Fixed at 110.3 MHz, the Other Channels Are Frequency Swept
–60
–65
–70
–75
–80
–85
600
500
400
300
200
100
–45
–50
–55
–60
–65
–70
–75
0
500
2 CHANNELS ON
1 CHANNEL ON
25.3
1.1
SINGLE DAC POWER PLANE
Figure 21. Averaged Channel SFDR vs. f
450
50.3
FREQUENCY OF COUPLING SPUR (MHz)
REFERENCE CLOCK FREQUENCY (MHz)
400
15.1
75.3
SEPARATED DAC POWER PLANES
350
Power On/Off
100.3
40.1
f
300
OUT
(MHz)
125.3
250
75.1
SFDR AVERAGED
200
150.3
100.3
150
175.3
OUT
100
200.3
AD9958
200.3
50