AD9958BCPZ Analog Devices Inc, AD9958BCPZ Datasheet - Page 27

IC DDS DUAL 500MSPS DAC 56LFCSP

AD9958BCPZ

Manufacturer Part Number
AD9958BCPZ
Description
IC DDS DUAL 500MSPS DAC 56LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9958BCPZ

Design Resources
Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186)
Resolution (bits)
10 b
Master Fclk
500MHz
Tuning Word Width (bits)
32 b
Voltage - Supply
1.71 V ~ 1.96 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-LFCSP
Pll Type
Frequency Synthesis
Frequency
500MHz
Supply Current
105mA
Supply Voltage Range
1.71V To 1.89V
Digital Ic Case Style
LFCSP
No. Of Pins
56
Operating Temperature Range
-40°C To +85°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9958/PCBZ - BOARD EVALUATION FOR AD9958
Lead Free Status / Rohs Status
Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9958BCPZ
Manufacturer:
ADI
Quantity:
636
Part Number:
AD9958BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
SWEEP AND PHASE ACCUMULATOR CLEARING
FUNCTIONS
The AD9958 allows two different clearing functions. The first
is a continuous zeroing of the sweep logic and phase accumula-
tor (clear and hold). The second is a clear and release or automatic
zeroing function. CFR[4] is the autoclear sweep accumulator bit
and CFR[2] is the autoclear phase accumulator bit. The continuous
clear bits are located in CFR, where CFR[3] clears the sweep
accumulator and CFR[1] clears the phase accumulator.
FTW1
FTW0
FTW1
FTW0
f
f
OUT
OUT
SINGLE-TONE
SINGLE-TONE
MODE
MODE
P2 = 0
P2 = 0
AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RDW<31:0>
AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FDW<31:0>
A
A
P2 = 1
Figure 39. Linear Sweep Mode (No-Dwell Disabled)
Figure 38. Linear Sweep Mode (No-Dwell Enabled)
LINEAR SWEEP MODE ENABLE—NO-DWELL BIT SET
LINEAR SWEEP MODE
P2 = 0
P2 = 1
B
Rev. A | Page 27 of 44
A
P2 = 1
Continuous Clear Bits
The continuous clear bits are static control signals that, when
active high, hold the respective accumulator at 0 while the bit is
active. When the bit goes low, the respective accumulator is
allowed to operate.
Clear and Release Bits
The autoclear sweep accumulator bit, when set, clears and
releases the sweep accumulator upon an I/O update or a change
in the profile input pins. The autoclear phase accumulator bit,
when set, clears and releases the phase accumulator upon an
I/O update or a change in the profile pins. The automatic
clearing function is repeated for every subsequent I/O update or
change in profile pins until the clear and release bits are reset
via the serial port.
B
B
P2 = 0
P2 = 0
A
P2 = 1
B
TIME
TIME
AD9958

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