E-STE100P STMicroelectronics, E-STE100P Datasheet

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... Serial to NRZI To NRZ Code Align Parallel Decoder NRZ To Manchester Link Pulse Encoder Detector STE100P TQFP64 (10x10x1.40mm) Part Number Package STE100P TQFP64 (*) TQFP64 E-STE100P Section 9 ) Binary To MLT3 Encoder TRANSMITTER 10/100 10 TX Filter Loopback Clock Generation Adaptive Binary To MLT3 Equalization Decoder BaseLine Clock Recovery ...

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... Mbps Speed LED: 100Mbps(on) or 10Mbps(off) ■ TX/RX Activity LED: Blinks at 10Hz when receiving, but not colliding ■ Link LED: On when a good link is detected, blinks when there activity ■ Full Duplex / Collision LED: On during Full Duplex operation. Blinks at 20Hz to indicate a collision ■ ...

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... Symbol (5B) Mode. These signals must be synchronized to the tx_clk. Transmit Enable. The MAC asserts this signal when it drives valid data on the txd inputs. This signal must be synchronized to the tx_clk. Transmit Clock. Normally the STE100P drives tx_clk. Refer to the Clock Requirements discussion in the Functional Description section ...

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... Interrupt is cleared by reading Register PR17. Requires MDC edge to output. 25 MHz reference clock input. When an external 25 MHz crystal is used, this pin will be connected to one terminal of it external 25 MHz clock source of oscillator is used, then this pin will be the input pin of it. 25 MHz reference clock output. When an external 25MHz crystal is used, this pin will be connected to another terminal of if ...

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... The status of this pin is latched into the PR20 bit 6 during power up/reset. LED display for Link Status. Blinks when there activity. This pin will be driven on continually when a good Link test is detected. The status of this pin is latched into the PR20 bit 5 during power up/reset. ...

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... Multi-Function pins. Each mf pin internally drives different configuration functions. The functions of the five mf inputs are as shown in the table below. The logic level of mf0-4 will determine the value that the affected bits will have upon reset of the STE100P. The operating functions of cfg0, cfg1, and fde change depending on the state of mf0 (Auto-Negotiation enabled or disabled) ...

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... Advertise 100 HD/FD Advertise 10 HD Advertise 10 HD/FD Advertise 10/100 HD Note: If pin 5, MF0 = 0, or ANE (pin MF0 / PR0:12 (Auto-Negotiation disabled), then PR4 bits 5-8 will contain the default value indicated in the table describing register PR4. 5.2 LED / PHY Address Interface The LED output pins can be used to drive LED’s directly, or can be used to provide status information to a network management device ...

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... REGISTERS AND DESCRIPTORS DESCRIPTION There are 11 registers with 16 bits each supported for the STE100P. These include 7 basic registers which are defined according to the clause 22 “Reconciliation Sublayer and Media Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of IEEE802 ...

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... TX _EN. De-assertion of TX_EN will cause the COL signal to be de-asserted. 6~0 --- Reserved R/W = Read/Write able Read Only. PR1- XSR, XCVR Status Register. All the bits of this register are read only 100BASE-T4 ability. Always 0, since STE100P has no T4 ability. 14 TXFD 100Base-TX full duplex ability ...

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... Jabber detection. 1: jabber condition is detected (10Base-T only). 0 EXT Extended register supporting. Always 1, since STE100P supports extended register LL* = Latching Low and clear by read. LH* = Latching High and clear by read. PR2- PID1, PHY Identifier 1 15~0 PHYID1 Part one of PHY Identifier. Assigned to the 3 Identifier (OUI). (The ST OUI is 0080E1 hex). ...

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... Remote Fault function. 1: with remote fault function. 12,11 --- Reserved 10 FC Flow Control function Ability. 1:supports PAUSE operation of flow control for full duplex link 100BASE-T4 Ability. Always 0: since STE100P doesn’t have 100BASE-T4 ability. 8 TXF 100Base-TX Full duplex Ability. 1: with 100Base-TX full duplex ability. ...

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... Link Partner’s Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability STE100P’s next Page ability. Always 0, since STE100P without next page ability Page Received new page has been received new page has been received. ...

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... Interrupt source of Auto-Negotiation Page Received. 0: there is no Auto-Negotiation page received. 1: auto-negotiation page is received. 0 REF Interrupt source of Receive Error full. 0: the receive error number is less than 64 error packets are received High Latching and cleared by reading. PR18- XIE, XCVR Interrupt Enable Register 15~7 --- ...

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... ISOTX Transmit Isolation. When 1, isolate from MII and tx+/-. The bit will be set to one if the PHY address is set to 00000 at power- up/reset This bit must be 0 for normal operation 4~2 CMODE Reporting of current operation mode of transceiver. ...

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... Data code-groups Encoder: In normal MII mode application, the device receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the device on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100Base-TX. ...

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... Data conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3: After scrambled, the transmission data with 5B type in 25MHz will be converted to serial bit stream in 125MHz by the parallel to serial func- tion. After serialized, the transmission serial bit stream will be further converted from NRZ to NRZI format. ...

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... NRZI to NRZ converter. In the 100Base-TX remote loop-back operation, the data is received from rxp/rxn pins through receive path to the output of data and clock recover and then loop-back to the input of NRZI to MLT3 converter of transmit path then transmit out to the medium via the transmit line drivers. ...

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... Second, for software reset, when bit 15 of register PR0 is set to 1, the STE100P will reset entire circuits and registers to their default values, then clear the bit 15 of PR0 to 0, and set the RIP output pin 29 to logic 1. Both hardware and software reset operations initialize all registers to their default values. This process includes re-evaluation of all hardware-configurable registers ...

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... The Remote Fault bit remains at logic one until successful negotiation with the Link Code Word occurs. The bit will then return to 0. When the message is sent that the Remote Fault bit is set to logic one, the device will set the Remote Fault bit in the MII to logic one if the management function is present. ...

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... Input Differential Accept Peak Voltage Vidr10 Input Differential Reject Peak Voltage Vod10 Output Differential Peak Voltage Icc10 Supply Current 100Base-TX Voltage/Current Characteristics Vida100 Input Differential Accept Peak Voltage Vidr100 Input Differential Reject Peak Voltage Vod100 Output Differential Peak Voltage Icc100 Supply Current 20/31 -0 ...

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... Parameter X1 Specifications TX1d X1 Duty Cycle TX1p X1 Period TX1t X1 Tolerance TX1C X1 Load Capacitance L 10Base-T Normal Link Pulse (NLP) Timings Specifications TNPW NLP Width TNPC NLP Period Figure 8. Normal Link Pulse timings Tnpw Tnpc Table 8. AC Specifications Symbol Parameter Auto-Negotiation Fast Link Pulse(FLP) Timings Specifications ...

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... STE100P Figure 9. Fast Link Pulse timing Tflbw Table 8. AC Specifications Symbol Parameter 100Base-TX Transmitter AC Timings Specification Tjit TDP-TDN Differential Output Peak Jitter MII Management Clock Timing Specifications t1 MDC High Pulse Width t2 MDC Low Pulse Width t3 MDC Period t4 MDIO(I) Setup to MDC Rising ...

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... Figure 10. MII Management Clock Timing MDC MDIO(I) MDIO(O) Table 8. AC Specifications Symbol Parameter MII Receive Timing Specification t1 RX-ER, RX-DV, RXD[3:0] Setup to RX-CLK t2 RX-ER, RX-DV, RXD[3:0] Hold After RX-CLK t3 RX-CLK High Pulse Width (100 Mbits/s) RX-CLK High Pulse Width (10 Mbits/s) t4 RX-CLK Low Pulse Width (100 ...

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... STE100P Figure 11. MII Receive Timing Table 8. AC Specifications Symbol Parameter MII Transmit Timing Specification t1 TX-ER,TX-EN,TXD[3:0] Setup to TX-CLK Rise t2 TX-ER,TX-EN,TXD[3:0] Hold After TX-CLK Rise Figure 12. MII Transmit Timing 24/31 Test Condition Min Typ. Max. Units — ...

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... Receive Frame to Sampled Edge of RX-DV (100 Mbits/s) Receive Frame to Sampled Edge of RX-DV (10 Mbits/s) Rt2 Receive Frame to CRS High (100Mbits/s) Receive Frame to CRS High (10 Mbits/s) Rt3 End of Receive Frame to Sampled Edge of RX-DV (100 Mbits/s) End Receive Frame to Sampled Edge of RX-DV (10 Mbits/s) Rt4 ...

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... STE100P Table 8. AC Specifications Symbol Parameter Transmit Timing Specification t1 TX-EN Sampled to CRS High (100 Mbits/s) TX-EN Sampled to CRS High (10 Mbits/s) t2 TX-EN Sampled to CRS Low (100 Mbits/s) TX-EN Sampled to CRS Low (10 Mbits/s) t3 Transmit Latency (100 Mbits/s) Transmit Latency (10 Mbits/s) t4 Sampled TX-EN Inactive to End ...

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... TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. Sym Min Typ t2A ...

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... Figure 16. 10Base-T Half Duplex Transmit Timing TXP Table 10. Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TXP out (Tx latency) 28/31 Sym Min Typ t8A 10 - t8B ...

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... In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...

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... August 2004 September 2004 February 2005 30/31 15 Rev. A12 June 2003 has been migrated from ST-PRESS to EDOCS. 16 Changed the Style-sheet on the Rev. A13. 17 Wrong package corrected. 18 Due to Rev. 17 content was partially wrong. Now fixed. 19 Added part number “E-STE100P” (ECOPACK). Description of Changes ...

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