E-STE100P STMicroelectronics, E-STE100P Datasheet - Page 5

• Manufacturer Part Number: E-STE100P
• Description: IC TRANSCEIVER 3.3V 64 TQFP
• Manufacturer: STMicroelectronics
• Type: Transceiverr

Specifications of E-STE100P

• Number Of Drivers/receivers: 1/1
• Protocol: MII
• Voltage - Supply: 3.15 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2143; STE100P

Table 2. Pin Description (continued)
8, 30,31,
Pin No.
26, 33
15
38
37
36
35
34
64
63
28
29
32
27
pwrdwn
test_se
Name
ledr10
reset
ledtr
cfg0
cfg1
test,
ledc
leds
ledl
iref
rip
nc
Type
I/O
I/O
I/O
I/O
O
O
I
I
I
I
Reference Resistor connecting pin for reference current, directly connect a 5KΩ ±
1% resistor to Vss.
LED display for 10Ms/s link status. This pin will be driven on continually when
10Mb/s network operating speed is detected.
The pull-up/pull-down status of this pin is latched into the PR20 bit 7 during
power up/reset.
LED display for Tx/Rx Activity status. This pin will be driven on at a 10 Hz blinking
frequency when either effective receiving or transmitting is detected.
The status of this pin is latched into the PR20 bit 6 during power up/reset.
LED display for Link Status. Blinks when there is TX or RX activity. This pin will be
driven on continually when a good Link test is detected.
The status of this pin is latched into the PR20 bit 5 during power up/reset.
continually when a full duplex configuration is detected. This pin will be driven on
at a 20 Hz blinking frequency when a collision status is detected in the half duplex
configuration.
The status of this pin is latched into the PR20 bit 4 during power up/reset.
100Mb/s network operating speed is detected.
The status of this pin is latched into the PR20 bit 3 during power up/reset.
Configuration Control 0.
When A/N is enabled, cfg0 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See Table 2)
When A/N is disabled, cfg1 disables mlt3 and directly affects PR19:0
When cfg0 is Low, mlt3 encoder/decoder is enabled and PR19:1 =0.
When cfg0 is High, mlt3 encoder/decoder is bypassed and PR19:1 = 1.
Configuration Control 1.
When A/N is enabled, cfg1 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See Table 2)
When A/N is disabled, CFG1 enables Loopback mode and directly affects PR0
bit 14.
When cfg1 is Low, Loopback mode is disabled and PR0:14 = 0.
When cfg1 is High, Loopback mode is enabled and PR0:14 = 1.
Reset (Active-Low). This input must be held low for a minimum of 1 ms to reset
the STE100P. During Power-up, the STE100P will be reset regardless of the state
of this pin, and this reset will not be complete until after >1ms.
Reset In Progress. This output is used to indicate when the device has
completed power-up/reset and the registers and functions can be accessed.
When rip is High, power-up/reset has been successful and the device can be
used normally
When rip is Low, device reset is not complete.
nc (No Connection)
Test pins. Should be tied to ground for normal operation
Power Down. When High, forces STE100P into Power Down mode. This pin is
OR’ed with the Power Down bit (PR0:11). During the Power Down mode, txp/txn
outputs and all LED outputs are 3-stated, and the MII interface is isolated.
LED display for Full Duplex or Collision status. This pin will be driven on
LED display for 100Ms/s link status. This pin will be driven on continually when
Description
STE100P
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