DSPIC30F3011-30I/PT Microchip Technology Inc., DSPIC30F3011-30I/PT Datasheet - Page 51

• Manufacturer Part Number: DSPIC30F3011-30I/PT
• Description: 16 BIT MCU/DSP 44LD 30MIPS 24 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F3011-30I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 24K Bytes
• Ram Size: 1K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Once
addresses into a buffer should not be changed.
Although all EAs will continue to be generated correctly
irrespective of offset sign, only one address boundary
is checked for each type of buffer. Thus, if a buffer is set
up to be an incrementing buffer by choosing an appro-
priate starting address, then correction of the effective
address will be performed by the AGU at the upper
address boundary, but no address correction will occur
if the EA crosses the lower address boundary. Similarly,
for a decrementing boundary, address correction will
be performed by the AGU at the lower address bound-
ary, but no address correction will take place if the EA
crosses the upper address boundary. The circular
buffer pointer may be freely modified in both directions
without a possibility of out-of-range address access
only when the start address satisfies the condition for
an incrementing buffer (last ‘N’ bits are zeroes) and the
end address satisfies the condition for a decrementing
buffer (last ‘N’ bits are ones). Thus, the modulo
addressing capability is truly bi-directional only for
modulo-2 length buffers.
4.5
Bit-Reversed addressing is intended to simplify data re-
ordering for radix-2 FFT algorithms. It is supported by
the X WAGU only (i.e., for data writes only).
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.5.1
Bit-Reversed addressing is enabled when:
1.
FIGURE 4-3:
 2004 Microchip Technology Inc.
BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not be accessed using bit-reversed addressing)
and
b15 b14 b13 b12
b15 b14 b13 b12
configured,
Bit-Reversed Addressing
BIT-REVERSED ADDRESSING
IMPLEMENTATION
the
BIT-REVERSED ADDRESS EXAMPLE
b11 b10 b9 b8
b11 b10 b9 b8
direction
of
b7 b6 b5 b4
b7 b6 b5 b1
successive
Pivot Point
Preliminary
b3 b2 b1
b2 b3 b4
Sequential Address
Bit-Reversed Address
2.
3.
If the length of a bit-reversed buffer is M = 2
then the last ’N’ bits of the data buffer start address
must be zeros.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, bit-reversed addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other addressing mode or for
byte-sized data, and normal addresses will be gener-
ated instead. When bit-reversed addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the LS
bit of the EA is ignored (and always clear).
If bit-reversed addressing has already been enabled by
setting the BREN (XBREV<15>) bit, then a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
Note:
Note:
the BREN bit is set in the XBREV register and
the Addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
XB = 0x0008 for a 16-word Bit-Reversed Buffer
0
0
All Bit-Reversed EA calculations assume
word sized data (LS bit of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo
addressing
together. In the event that the user
attempts to do this, bit reversed address-
ing will assume priority when active for the
X WAGU, and X WAGU modulo address-
ing will be disabled. However, modulo
addressing will continue to function in the
X RAGU.
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
addressing
should
dsPIC30F
not
and
DS70082G-page 49
be
bit-reversed
enabled
N
bytes,