DSPIC30F6010A-30I/PF Microchip Technology Inc., DSPIC30F6010A-30I/PF Datasheet - Page 20
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DSPIC30F6010A-30I/PF
Manufacturer Part Number
DSPIC30F6010A-30I/PF
Description
16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F6010A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6010A-30I/PF
A/d Inputs
16-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
4K Bytes
Input Output
68
Interface
CAN, I2C, SPI, UART/USART
Ios
68
Memory Type
Flash
Number Of Bits
16
Package Type
80-pin TQFP
Programmable Memory
144K Bytes
Ram Size
8K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Manufacturer
Quantity
Price
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dsPIC30F6010A/6015
2.4.1
The 17x17-bit multiplier is capable of signed or
unsigned operations and can multiplex its output using
a scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the mul-
tiplier input value. The output of the 17x17-bit multiplier/
scaler is a 33-bit value, which is sign-extended to
40 bits. Integer data is inherently represented as a
signed two’s complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
an N-bit two’s complement integer is -2
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF), including 0. For a 32-bit integer, the
data range is -2,147,483,648 (0x8000 0000) to
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional multipli-
cation, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit
(QX format). The range of an N-bit two’s complement
fraction with this implied radix point is -1.0 to (1-2
For a 16-bit fraction, the Q15 data range is -1.0
(0x8000) to 0.999969482 (0x7FFF), including 0 and
has a precision of 3.01518x10
16x16 multiply operation generates a 1.31 product,
which has a precision of 4.65661x10
The same multiplier is used to support the MCU multi-
ply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies.
The MUL instruction may be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
2.4.2
The data accumulator consists of a 40-bit adder/sub-
tractor with automatic sign extension logic. It can select
one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation destina-
tion. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
DS70150B-page 18
MULTIPLIER
DATA ACCUMULATORS AND
ADDER/SUBTRACTOR
-5
. In Fractional mode, a
-10
.
N-1
to 2
N-1
1-N
– 1.
).
2.4.2.1
The adder/subtractor is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active-high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active-low and the
other input is complemented. The adder/subtractor
generates Overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS register.
• Overflow from bit 39: this is a catastrophic
• Overflow into guard bits 32 through 39: this is a
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow. They are:
1.
2.
3.
4.
5.
6.
The OA and OB bits are modified each time data passes
through the adder/subtractor. When set, they indicate
that the most recent operation has overflowed into the
accumulator guard bits (bits 32 through 39). The OA and
OB bits can also optionally generate an arithmetic warn-
ing trap when set and the corresponding overflow trap
flag enable bit (OVATE, OVBTE) in the INTCON1 regis-
ter (refer to Section 5.0 “Interrupts”) is set. This allows
the user to take immediate action, for example, to correct
system gain.
overflow in which the sign of the accumulator is
destroyed.
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
Adder/Subtractor, Overflow and
Saturation
© 2006 Microchip Technology Inc.