DSPIC30F6010A-30I/PF Microchip Technology Inc., DSPIC30F6010A-30I/PF Datasheet - Page 99

• Manufacturer Part Number: DSPIC30F6010A-30I/PF
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6010A-30I/PF

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

15.4
Center-aligned PWM signals are produced by the mod-
ule when the PWM time base is configured in an Up/
Down Counting mode (see Figure 15-3).
The PWM compare output is driven to the active state
when the value of the Duty Cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is equal to
the value held in the PTPER register.
FIGURE 15-3:
15.5
There are four 16-bit Special Function Registers
(PDC1, PDC2, PDC3 and PDC4) used to specify duty
cycle values for the PWM module.
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The Duty Cycle registers are 16-bits wide. The
LSb of a Duty Cycle register determines whether the
PWM edge occurs in the beginning. Thus, the PWM
resolution is effectively doubled.
© 2006 Microchip Technology Inc.
PTPER
Duty
Cycle
0
Center-Aligned PWM
PWM Duty Cycle Comparison
Units
Period/2
CENTER-ALIGNED PWM
Period
PTMR
Value
dsPIC30F6010A/6015
15.5.1
The four PWM Duty Cycle registers are double-
buffered to allow glitchless updates of the PWM
outputs. For each duty cycle, there is a Duty Cycle reg-
ister that is accessible by the user and a second Duty
Cycle register that holds the actual compare value
used in the present PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER reg-
ister occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
Duty Cycle registers when the PWM time base is dis-
abled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
When the PWM time base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the Duty
Cycle registers when the PWM time base is disabled
(PTEN = 0).
15.5.2
When the Immediate Update Enable bit is set (IUE = 1),
any write to the Duty Cycle registers will update the
new duty cycle value immediately. This feature gives
the option to the user to allow immediate updates of the
active PWM Duty Cycle registers instead of waiting for
the end of the current time base period. System stabil-
ity is improved in closed loop servo applications by
reducing the delay between system observation and
the issuance of system corrective commands when
immediate updates are enabled (IUE = 1).
If the PWM output is active at the time the new duty
cycle is written and the new duty cycle is less than the
current time base value, the PWM pulse width will be
shortened. If the PWM output is active at the time the
new duty cycle is written and the new duty cycle is
greater than the current time base value, the PWM
pulse width will be lengthened.
If the PWM output is inactive at the time the new duty
cycle is written and the new duty cycle is greater than
the current time base value, the PWM output will
become active immediately and will remain active for
the new written duty cycle value.
DUTY CYCLE REGISTER BUFFERS
DUTY CYCLE IMMEDIATE
UPDATES
DS70150B-page 97