PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 140

• Manufacturer Part Number: PIC18F4550-I/PT
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
14.1
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
FIGURE 14-1:
FIGURE 14-2:
DS39632C-page 138
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
Timer3 Operation
T1OSI
T1OSI
CCP1/CCP2 Select from T3CON<6,3>
CCP1/CCP2 Select from T3CON<6,3>
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Special Event Trigger
Timer1 Oscillator
Timer1 Oscillator
TIMER3 BLOCK DIAGRAM
T1OSCEN
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1OSCEN
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
(1)
(1)
TMR3CS
TMR3CS
Clock
Clock
Internal
Internal
F
F
OSC
OSC
/4
/4
Preliminary
1
0
1
0
Timer1 Clock Input
Timer1 Clock Input
Clear TMR3
Clear TMR3
Prescaler
Prescaler
1, 2, 4, 8
1, 2, 4, 8
cycle (F
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As with Timer1, the RC1/T1OSI/UOE and RC0/
T1OSO/T13CKI pins become inputs when the Timer1
oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
2
2
OSC
TMR3L
TMR3L
/4). When the bit is set, Timer3 increments
8
8
Synchronize
Synchronize
Sleep Input
Sleep Input
Detect
Detect
High Byte
High Byte
TMR3H
TMR3
TMR3
8
© 2006 Microchip Technology Inc.
8
8
1
0
1
0
Set
TMR3IF
on Overflow
Read TMR1L
Write TMR1L
Internal Data Bus
Set
TMR3IF
on Overflow
Timer3
Timer3
On/Off
On/Off