PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 39

• Manufacturer Part Number: PIC18F4550-I/PT
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 3-1:
FIGURE 3-2:
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When using the INTRC source, this mode provides the
best power conservation of all the Run modes while still
executing code. It works well for user applications
which are not highly timing sensitive or do not require
high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distin-
guishable differences between the PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
© 2006 Microchip Technology Inc.
Note 1:
Peripheral
Program
Counter
T1OSI
OSC1
Clock
Clock
Note 1:
CPU
CPU Clock
RC_RUN MODE
Peripheral
PLL Clock
Program
Counter
Output
T1OSI
OSC1
Clock
Clock transition typically occurs within 2-4 T
2:
SCS1:SCS0 bits Changed
Q1
T
Clock transition typically occurs within 2-4 T
OST
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q2
= 1024 T
PC
Q3
Q4
OSC
Q1
Q1
; T
T
PLL
OST (1)
1
= 2 ms (approx). These intervals are not shown to scale.
PC
Q2
2
PIC18F2455/2550/4455/4550
Clock Transition
T
3
PLL
OSTS bit Set
Q3
OSC
Preliminary
(1)
.
OSC
Q4
.
PC + 2
(1)
n-1
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTOSC multiplexer (see Figure 3-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.
Q1
1
n
Note:
Transition
2
Clock
(2)
n-1 n
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
PC + 2
Q2
DD
Q3
/F
Q2
OSC
Q4
Q3 Q4
specifications are violated.
Q1
Q1
DD
PC + 4
is less than 3V, it is
Q2
Q2
PC + 4
DS39632C-page 37
Q3
Q3
DD
.