PIC18F6520-I/PT Microchip Technology Inc., PIC18F6520-I/PT Datasheet
PIC18F6520-I/PT
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PIC18F6520-I/PT Summary of contents
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... PIC18F6520/8520/6620/8620/6720/8720 256 Kbit to 1 Mbit Enhanced Flash 2004 Microchip Technology Inc. 64/80-Pin High-Performance, Microcontrollers with A/D Data Sheet DS39609B ...
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... The Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs ® code hopping devices, Serial EE OQ EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. ...
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... PIC18F8620 64K 32768 3840 PIC18F8720 128K 65536 3840 2004 Microchip Technology Inc. PIC18F6520/8520/6620/ 8620/6720/8720 Analog Features: • 10-bit 16-channel Analog-to-Digital Converter (A/D): - Conversion available during Sleep • Programmable 16-level Low-Voltage Detection (LVD) module: - Supports interrupt on Low-Voltage Detection • Programmable Brown-out Reset (PBOR) • ...
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... PP RG4/CCP5 RF7/SS 11 RF6/AN11 12 RF5/AN10/CV 13 REF RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT 16 Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set. DS39609B-page PIC18F6520 42 41 PIC18F6620 40 PIC18F6720 2004 Microchip Technology Inc. RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC V SS OSC2/CLKO/RA6 OSC1/CLKI V DD RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL ...
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... PIC18F6520/8520/6620/8620/6720/8720 Pin Diagrams (Continued) 80-Pin TQFP RH2/A18 1 RH3/A19 2 (3) RE1/WR/AD9 3 (3) RE0/RD/AD8 4 RG0/CCP3 5 RG1/TX2/CK2 6 RG2/RX2/DT2 7 RG3/CCP4 8 MCLR RG4/CCP5 RF7/SS 13 RF6/AN11 14 RF5/AN10/CV REF 15 RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 RH7/AN15 19 RH6/AN14 20 Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set. 2: CCP2 is multiplexed by default with RE7 when the device is configured in Microcontroller mode. ...
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... Appendix C: Conversion Considerations ........................................................................................................................................... 362 Appendix D: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 362 Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 363 Index .................................................................................................................................................................................................. 365 On-Line Support................................................................................................................................................................................. 375 Systems Information and Upgrade Hot Line ...................................................................................................................................... 375 Reader Response .............................................................................................................................................................................. 376 PIC18F6520/8520/6620/8620/6720/8720 Product Identification System .......................................................................................... 377 DS39609B-page 4 2004 Microchip Technology Inc. ...
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... PIC18F6520/8520/6620/8620/6720/8720 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 6 2004 Microchip Technology Inc. ...
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... PIC18F6520/8520/6620/8620/6720/8720 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6520 • PIC18F8520 • PIC18F6620 • PIC18F8620 • PIC18F6720 • PIC18F8720 This family offers the same advantages of all PIC18 microcontrollers – namely, high performance at an economical price – with the addition of high endurance Enhanced Flash program memory ...
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... PIC18FX620 devices and 128 Kbytes for PIC18FX720 devices) 2. Data RAM (2048 bytes for PIC18FX520 devices, 3840 bytes for PIC18FX620 and PIC18FX720 devices) TABLE 1-1: PIC18FXX20 DEVICE FEATURES Features PIC18F6520 Operating Frequency DC – 40 MHz Program Memory 32K (Bytes) Program Memory 16384 (Instructions) ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 1-1: PIC18F6X20 BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 PCLATU PCU Program Counter Address Latch 31 Level Stack Program Memory Data Latch Table Latch 8 16 Instruction Decode & Control Power-up OSC2/CLKO Timer OSC1/CLKI Timing Oscillator Generation Start-up Timer Power-on Reset Watchdog ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 1-2: PIC18F8X20 BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 PCLATU PCU Program Counter Address Latch 31 Level Stack Program Memory Data Latch Table Latch 8 16 (1) AD15:AD0, A19:A16 Instruction Decode & Control Power-up OSC2/CLKO OSC1/CLKI Oscillator Timing Generation Start-up Timer Power-on Watchdog ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18F6X20 PIC18F8X20 MCLR MCLR V PP OSC1/CLKI 39 OSC1 CLKI OSC2/CLKO/RA6 40 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except Microcontroller) ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RA0/AN0 24 RA0 AN0 RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4/LVDIN 27 RA5 AN4 LVDIN RA6 Legend: TTL = TTL compatible input ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RB0/INT0 48 RB0 INT0 RB1/INT1 47 RB1 INT1 RB2/INT2 46 RB2 INT2 RB3/INT3/CCP2 45 RB3 INT3 (1) CCP2 RB4/KBI0 44 RB4 KBI0 RB5/KBI1/PGM 43 RB5 KBI1 PGM RB6/KBI2/PGC 42 RB6 KBI2 PGC RB7/KBI3/PGD 37 RB7 KBI3 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/CCP2 29 RC1 T1OSI (2) CCP2 RC2/CCP1 33 RC2 CCP1 RC3/SCK/SCL 34 RC3 SCK SCL RC4/SDI/SDA 35 RC4 SDI SDA RC5/SDO 36 RC5 SDO RC6/TX1/CK1 31 RC6 TX1 CK1 RC7/RX1/DT1 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RD0/PSP0/AD0 58 RD0 PSP0 (3) AD0 RD1/PSP1/AD1 55 RD1 PSP1 (3) AD1 RD2/PSP2/AD2 54 RD2 PSP2 (3) AD2 RD3/PSP3/AD3 53 RD3 PSP3 (3) AD3 RD4/PSP4/AD4 52 RD4 PSP4 (3) AD4 RD5/PSP5/AD5 51 RD5 PSP5 (3) AD5 RD6/PSP6/AD6 50 RD6 PSP6 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RE0/RD/AD8 2 RE0 RD (3) AD8 RE1/WR/AD9 1 RE1 WR (3) AD9 RE2/CS/AD10 64 RE2 CS (3) AD10 RE3/AD11 63 RE3 (3) AD11 RE4/AD12 62 RE4 AD12 RE5/AD13 61 RE5 (3) AD13 RE6/AD14 60 RE6 (3) AD14 RE7/CCP2/AD15 59 RE7 (1,4) ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RF0/AN5 18 RF0 AN5 RF1/AN6/C2OUT 17 RF1 AN6 C2OUT RF2/AN7/C1OUT 16 RF2 AN7 C1OUT RF3/AN8 15 RF1 AN8 RF4/AN9 14 RF1 AN9 RF5/AN10/CV 13 REF RF1 AN10 CV REF RF6/AN11 12 RF6 AN11 RF7/SS 11 RF7 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RG0/CCP3 3 RG0 CCP3 RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 5 RG2 RX2 DT2 RG3/CCP4 6 RG3 CCP4 RG4/CCP5 8 RG4 CCP5 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RH0/A16 — RH0 A16 RH1/A17 — RH1 A17 RH2/A18 — RH2 A18 RH3/A19 — RH3 A19 RH4/AN12 — RH4 AN12 RH5/AN13 — RH5 AN13 RH6/AN14 — RH6 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X20 PIC18F8X20 RJ0/ALE — RJ0 ALE RJ1/OE — RJ1 OE RJ2/WRL — RJ2 WRL RJ3/WRH — RJ3 WRH RJ4/BA0 — RJ4 BA0 RJ5/CE — RJ5 CE RJ6/LB — RJ6 LB RJ7/UB — ...
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... PIC18F6520/8520/6620/8620/6720/8720 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18FXX20 devices can be operated in eight different oscillator modes. The user can program three configuration bits (FOSC2, FOSC1 and FOSC0) to select one of these eight modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HS+PLL High-Speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Ranges Tested: Mode Freq kHz 15-22 pF 200 kHz XT 1 MHz 15- MHz HS 4 MHz 8 MHz 15- MHz Capacitor values are for design guidance only. These capacitors were tested with the above crystal frequencies for basic start-up and operation. These values are not optimized ...
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... PIC18F6520/8520/6620/8620/6720/8720 2.4 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is a maximum 1.5 s start-up required after a Power-on Reset, or wake-up from Sleep mode ...
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... PIC18F6520/8520/6620/8620/6720/8720 2.6 Oscillator Switching Feature The PIC18FXX20 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. For the PIC18FXX20 devices, this alternate clock source is the Timer1 oscillator low-frequency crystal (32 kHz, for example) has been attached to the ...
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... PIC18F6520/8520/6620/8620/6720/8720 2.6.1 SYSTEM CLOCK SWITCH BIT The system clock source switching is performed under software control. The system clock switch bit, SCS (OSCCON<0>), controls the clock switching. When the SCS bit is ‘0’, the system clock source comes from the main oscillator that is selected by the FOSC configura- tion bits in Configuration Register 1H ...
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... PIC18F6520/8520/6620/8620/6720/8720 2.6.2 OSCILLATOR TRANSITIONS PIC18FXX20 devices contain circuitry to prevent “glitches” when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources ...
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... PIC18F6520/8520/6620/8620/6720/8720 If the main oscillator is configured for HS-PLL mode, an oscillator start-up time (T ), plus an additional PLL OST time-out (T ), will occur. The PLL time-out is typically PLL 2 ms and allows the PLL to lock to the main oscillator FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL) ...
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... PIC18F6520/8520/6620/8620/6720/8720 2.7 Effects of Sleep Mode on the On-Chip Oscillator When the device executes a SLEEP instruction, the on- chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor ...
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... PIC18F6520/8520/6620/8620/6720/8720 3.0 RESET The PIC18FXX20 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (PBOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset Most registers are unaffected by a Reset ...
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... PIC18F6520/8520/6620/8620/6720/8720 3.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when V rise is detected. To take advantage of the POR DD circuitry, tie the MCLR pin through resistor This will eliminate external RC DD components usually needed to create a Power-on Reset delay. A minimum rise rate for V (parameter D004). For a slow rise time, see Figure 3-2. ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration PWRTE = 0 (1) HS with PLL enabled 1024 T + 2ms HS, XT 1024 External Note the nominal time required for the 4xPLL to lock the nominal power-up timer delay, if implemented the recovery time from Sleep. There is no recovery time from oscillator switch. ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices TOSU PIC18F6X20 PIC18F8X20 TOSH PIC18F6X20 PIC18F8X20 TOSL PIC18F6X20 PIC18F8X20 STKPTR PIC18F6X20 PIC18F8X20 PCLATU PIC18F6X20 PIC18F8X20 PCLATH PIC18F6X20 PIC18F8X20 PCL PIC18F6X20 PIC18F8X20 TBLPTRU PIC18F6X20 PIC18F8X20 TBLPTRH PIC18F6X20 PIC18F8X20 TBLPTRL PIC18F6X20 PIC18F8X20 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices FSR1H PIC18F6X20 PIC18F8X20 FSR1L PIC18F6X20 PIC18F8X20 BSR PIC18F6X20 PIC18F8X20 INDF2 PIC18F6X20 PIC18F8X20 POSTINC2 PIC18F6X20 PIC18F8X20 POSTDEC2 PIC18F6X20 PIC18F8X20 PREINC2 PIC18F6X20 PIC18F8X20 PLUSW2 PIC18F6X20 PIC18F8X20 FSR2H PIC18F6X20 PIC18F8X20 FSR2L PIC18F6X20 PIC18F8X20 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADRESH PIC18F6X20 PIC18F8X20 ADRESL PIC18F6X20 PIC18F8X20 ADCON0 PIC18F6X20 PIC18F8X20 ADCON1 PIC18F6X20 PIC18F8X20 ADCON2 PIC18F6X20 PIC18F8X20 CCPR1H PIC18F6X20 PIC18F8X20 CCPR1L PIC18F6X20 PIC18F8X20 CCP1CON PIC18F6X20 PIC18F8X20 CCPR2H PIC18F6X20 PIC18F8X20 CCPR2L PIC18F6X20 PIC18F8X20 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR3 PIC18F6X20 PIC18F8X20 PIR3 PIC18F6X20 PIC18F8X20 PIE3 PIC18F6X20 PIC18F8X20 IPR2 PIC18F6X20 PIC18F8X20 PIR2 PIC18F6X20 PIC18F8X20 PIE2 PIC18F6X20 PIC18F8X20 IPR1 PIC18F6X20 PIC18F8X20 PIR1 PIC18F6X20 PIC18F8X20 PIE1 PIC18F6X20 PIC18F8X20 MEMCON PIC18F6X20 PIC18F8X20 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PORTJ PIC18F6X20 PIC18F8X20 PORTH PIC18F6X20 PIC18F8X20 PORTG PIC18F6X20 PIC18F8X20 PORTF PIC18F6X20 PIC18F8X20 PORTE PIC18F6X20 PIC18F8X20 PORTD PIC18F6X20 PIC18F8X20 PORTC PIC18F6X20 PIC18F8X20 PORTB PIC18F6X20 PIC18F8X20 (5,6) PORTA PIC18F6X20 PIC18F8X20 TMR4 ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 3-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. ...
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... NOP instruction). Devices in the PIC18FXX20 family can be divided into three groups, based on program memory size. The PIC18FX520 devices (PIC18F6520 and PIC18F8520) have 32 Kbytes of on-chip Flash memory, equivalent to 16,384 single-word instructions. The PIC18FX620 devices ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FXX20 DEVICES PC<20:0> CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 31 000000h 000008h 000018h On-Chip Flash Program Memory On-Chip Flash 007FFFh Program Memory 008000h Read ‘0’ 1FFFFFh 200000h PIC18FX520 PIC18FX620 (32 Kbyte) (64 Kbyte) Note: Size of memory regions not to scale ...
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... Boot+1 External Program Memory 1FFFFFh 1FFFFFh External On-Chip Memory Flash Boundary Values for Microprocessor with Boot Block, Microcontroller and Extended Microcontroller modes Device Boot PIC18F6520 0007FFh PIC18F6620 0001FFh PIC18F6720 0001FFh PIC18F8520 0007FFh PIC18F8620 0001FFh PIC18F8720 0001FFh Note 1: PIC18F6X20 devices are included here for completeness, to show the boundaries of their Boot Blocks and program memory spaces. ...
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... PIC18F6520/8520/6620/8620/6720/8720 4.2 Return Address Stack The return address stack allows any combination program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions ...
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... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 4-2: STKPTR REGISTER R/C-0 (1) STKFUL STKUNF bit 7 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ ...
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... PIC18F6520/8520/6620/8620/6720/8720 4.3 Fast Register Stack A “fast interrupt return” option is available for interrupts. A Fast Register Stack is provided for the Status, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt ...
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... PIC18F6520/8520/6620/8620/6720/8720 4.6 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined, such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle instruction causes the program counter to change (e ...
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... PIC18F6520/8520/6620/8620/6720/8720 4.7.1 TWO-WORD INSTRUCTIONS The PIC18FXX20 devices have four two-word instruc- tions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruc- tion ...
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... PIC18F6520/8520/6620/8620/6720/8720 4.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The data memory map is in turn divided into 16 banks of 256 bytes each. The lower 4 bits of the Bank Select Register (BSR< ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-6: DATA MEMORY MAP FOR PIC18FX520 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh = 0011 00h Bank 3 to Bank 6 = 0110 FFh 00h = 0111 Bank 7 FFh = 1000 Bank 8 to Bank 14 = 1110 00h = 1111 Bank 15 ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-7: DATA MEMORY MAP FOR PIC18FX620 AND PIC18FX720 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh = 0100 Bank 4 = 0101 Bank 5 to Bank 13 = 1101 00h = 1110 Bank 14 FFh 00h = 1111 ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP Address Name Address FFFh TOSU FDFh FFEh TOSH FDEh POSTINC2 FFDh TOSL FDDh POSTDEC2 FFCh STKPTR FDCh FFBh PCLATU FDBh FFAh PCLATH FDAh FF9h PCL FD9h FF8h TBLPTRU FD8h FF7h TBLPTRH FD7h FF6h TBLPTRL ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address (1) F7Fh — F5Fh (1) F7Eh — F5Eh (1) F7Dh — F5Dh (1) F7Ch — F5Ch (1) F7Bh — F5Bh (1) F7Ah — F5Ah (1) F79h — F59h F78h TMR4 F58h F77h PR4 F57h F76h T4CON F56h ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: REGISTER FILE SUMMARY File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF — PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by value in WREG FSR2H — ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 CCPR3H Capture/Compare/PWM Register 3 High Byte CCPR3L Capture/Compare/PWM Register 3 Low Byte CCP3CON — — DC3B1 CVRCON CVREN CVROE CVRR CMCON C2OUT C1OUT C2INV TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 (3) LATJ Read PORTJ Data Latch, Write PORTJ Data Latch (3) LATH Read PORTH Data Latch, Write PORTH Data Latch LATG — — LATF Read PORTF Data Latch, Write PORTF Data Latch ...
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... PIC18F6520/8520/6620/8620/6720/8720 4.10 Access Bank The Access Bank is an architectural enhancement, which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: • Intermediate computational values • Local variables of subroutines • ...
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... PIC18F6520/8520/6620/8620/6720/8720 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that read or written. Since this pointer is in RAM, the contents can be modified by the program ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-9: INDIRECT ADDRESSING OPERATION Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 4-10: INDIRECT ADDRESSING 11 Note 1: For register file map detail, see Table 4-2. DS39609B-page 58 0h RAM Address FFFh 12 File Address = Access of an Indirect Addressing Register FSR File Indirect Addressing ...
Page 61
... PIC18F6520/8520/6620/8620/6720/8720 4.13 Status Register The Status register, shown in Register 4-3, contains the arithmetic status of the ALU. The Status register can be the destination for any instruction, as with any other reg- ister. If the Status register is the destination for an instruction that affects the Z, DC bits, then the write to these five bits is disabled ...
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... PIC18F6520/8520/6620/8620/6720/8720 4.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 4-4: RCON REGISTER R/W-0 IPEN ...
Page 63
... PIC18F6520/8520/6620/8620/6720/8720 5.0 FLASH PROGRAM MEMORY The Flash program memory is readable, writable and erasable, during normal operation over the entire V range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time ...
Page 64
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 5-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section 5.5 “Writing to Flash Program Memory”. ...
Page 65
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘ ...
Page 66
... PIC18F6520/8520/6620/8620/6720/8720 5.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 5.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory ...
Page 67
... PIC18F6520/8520/6620/8620/6720/8720 5.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 5-4: READS FROM FLASH PROGRAM MEMORY (Even Byte Address) ...
Page 68
... PIC18F6520/8520/6620/8620/6720/8720 5.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 69
... PIC18F6520/8520/6620/8620/6720/8720 5.5 Writing to Flash Program Memory The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding reg- isters needed to program the Flash memory. There are 8 holding registers used by the table writes for programming ...
Page 70
... PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D’64 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA READ_BLOCK ...
Page 71
... PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD BCF EECON1, CFGS BSF EECON1, WREN BCF INTCON, GIE MOVLW 55h MOVWF EECON2 Required MOVLW AAh Sequence MOVWF EECON2 BSF EECON1, WR NOP BSF INTCON, GIE DECFSZ COUNTER_HI BRA PROGRAM_LOOP ...
Page 72
... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 70 2004 Microchip Technology Inc. ...
Page 73
... PIC18F6520/8520/6620/8620/6720/8720 6.0 EXTERNAL MEMORY INTERFACE Note: The External Memory Interface is not implemented on PIC18F6X20 (64-pin) devices. The External Memory Interface is a feature of the PIC18F8X20 devices that allows the controller to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. The physical implementation of the interface uses 27 pins. These pins are reserved for external address/data bus functions ...
Page 74
... PIC18F6520/8520/6620/8620/6720/8720 If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports ...
Page 75
... PIC18F6520/8520/6620/8620/6720/8720 6.2 16-bit Mode The External Memory Interface implemented in PIC18F8X20 devices operates only in 16-bit mode. The mode selection is not software configurable, but is programmed via the configuration bits. The WM<1:0> bits in the MEMCON register determine three types of connections in 16-bit mode. They are referred to as: • ...
Page 76
... PIC18F6520/8520/6620/8620/6720/8720 6.2.2 16-BIT WORD WRITE MODE Figure 6-2 shows an example of 16-bit Word Write mode for PIC18F8X20 devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
Page 77
... PIC18F6520/8520/6620/8620/6720/8720 6.2.3 16-BIT BYTE SELECT MODE Figure 6-3 shows an example of 16-bit Byte Select mode for PIC18F8X20 devices. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle ...
Page 78
... PIC18F6520/8520/6620/8620/6720/8720 6.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 6-4 through Figure 6-6. FIGURE 6-4: EXTERNAL MEMORY BUS TIMING FOR Apparent Actual 00h A<19:16> ...
Page 79
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 6-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE 00h A<19:16> AD<15:0> 0003h 3AAAh CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC-2) Execution 2004 Microchip Technology Inc 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h ...
Page 80
... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 78 2004 Microchip Technology Inc. ...
Page 81
... PIC18F6520/8520/6620/8620/6720/8720 7.0 DATA EEPROM MEMORY The data EEPROM is readable and writable during normal operation over the entire V DD memory is not directly mapped in the register file space. Instead indirectly addressed through the Special Function Registers (SFR). There are five SFRs used to read and write the program and data EEPROM memory ...
Page 82
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘ ...
Page 83
... PIC18F6520/8520/6620/8620/6720/8720 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>), clear the CFGS EXAMPLE 7-1: DATA EEPROM READ MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to read ...
Page 84
... PIC18F6520/8520/6620/8620/6720/8720 7.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory ...
Page 85
... PIC18F6520/8520/6620/8620/6720/8720 TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Name Bit 7 Bit 6 Bit 5 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE EEADRH — — — EEADR EEPROM Address Register EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS — ...
Page 86
... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 84 2004 Microchip Technology Inc. ...
Page 87
... PIC18F6520/8520/6620/8620/6720/8720 8 HARDWARE MULTIPLIER 8.1 Introduction hardware multiplier is included in the ALU of the PIC18FXX20 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored in the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the ALUSTA register ...
Page 88
... PIC18F6520/8520/6620/8620/6720/8720 Example 8-3 shows the sequence unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 2 (ARG1H ARG2L 2 (ARG1L ARG2H 2 (ARG1L ARG2L) EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE ...
Page 89
... PIC18F6520/8520/6620/8620/6720/8720 9.0 INTERRUPTS The PIC18FXX20 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high or a low priority level. The high priority interrupt vector is at 000008h, while the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress ...
Page 90
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 9-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit ...
Page 91
... PIC18F6520/8520/6620/8620/6720/8720 9.1 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: INTCON REGISTER R/W-0 GIE/GIEH PEIE/GIEL bit 7 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN (RCON<7> Enables all unmasked interrupts 0 = Disables all interrupts When IPEN (RCON< ...
Page 92
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge ...
Page 93
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 INT2IP INT1IP bit 7 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt ...
Page 94
... PIC18F6520/8520/6620/8620/6720/8720 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Flag Registers (PIR1, PIR2 and PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 95
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 — CMIF bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIF: Comparator Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software The comparator input has not changed bit 5 Unimplemented: Read as ‘0’ ...
Page 96
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 — bit 7 bit 7- 6 Unimplemented: Read as ‘0’ bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = The USART2 receive buffer, RCREG, is full (cleared when RCREG is read The USART2 receive buffer is empty bit 4 ...
Page 97
... PIC18F6520/8520/6620/8620/6720/8720 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must be set to enable any of these peripheral interrupts ...
Page 98
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 — CMIE bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit ...
Page 99
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: USART2 Receive Interrupt Enable bit 1 = Enables the USART2 receive interrupt 0 = Disables the USART2 receive interrupt bit 4 TX2IE: USART2 Transmit Interrupt Enable bit ...
Page 100
... PIC18F6520/8520/6620/8620/6720/8720 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority Registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 101
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 — CMIP bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit ...
Page 102
... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: USART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: USART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit ...
Page 103
... PIC18F6520/8520/6620/8620/6720/8720 9.5 RCON Register The RCON register contains the IPEN bit, which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section 4.14 “RCON Register”. REGISTER 9-13: RCON REGISTER R/W-0 IPEN bit 7 bit 7 IPEN: Interrupt Priority Enable bit ...
Page 104
... PIC18F6520/8520/6620/8620/6720/8720 9.6 INT0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE ...
Page 105
... PIC18F6520/8520/6620/8620/6720/8720 10.0 I/O PORTS Depending on the device selected, there are either seven or nine I/O ports available on PIC18FXX20 devices. Some of their pins are multiplexed with one or more alternate functions from the other peripheral fea- tures on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin ...
Page 106
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS RD LATA Data Bus LATA or PORTA Q CK Data Latch TRISA Q CK Analog TRIS Latch Input Mode RD TRISA PORTA To A/D Converter and LVD Modules Note 1: I/O pins have protection diodes to V FIGURE 10-4: BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O) ...
Page 107
... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-1: PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 bit 0 TTL RA1/AN1 bit 1 TTL RA2/AN2/V - bit 2 TTL REF RA3/AN3/V + bit 3 TTL REF RA4/T0CKI bit 4 RA5/AN4/LVDIN bit 5 TTL OSC2/CLKO/RA6 bit 6 Legend: TTL = TTL input Schmitt Trigger input TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA ...
Page 108
... PIC18F6520/8520/6620/8620/6720/8720 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 109
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS (2) RBPU Data Bus WR Port WR TRIS RD TRIS RD Port INTx Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). FIGURE 10-7: BLOCK DIAGRAM OF RB3 PIN ...
Page 110
... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT0 bit 0 TTL/ST RB1/INT1 bit 1 TTL/ST RB2/INT2 bit 2 TTL/ST (3) RB3/INT3/CCP2 bit 3 TTL/ST RB4/KBI0 bit 4 TTL RB5/KBI1/PGM bit 5 TTL/ST RB6/KBI2/PGC bit 6 TTL/ST RB7/KBI3/PGD bit 7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. ...
Page 111
... PIC18F6520/8520/6620/8620/6720/8720 10.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
Page 112
... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type RC0/T1OSO/T13CKI bit 0 ST (1) RC1/T1OSI/CCP2 bit 1 ST RC2/CCP1 bit 2 ST RC3/SCK/SCL bit 3 ST RC4/SDI/SDA bit 4 ST RC5/SDO bit 5 ST RC6/TX1/CK1 bit 6 ST RC7/RX1/DT1 bit 7 ST Legend Schmitt Trigger input Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set. ...
Page 113
... PIC18F6520/8520/6620/8620/6720/8720 10.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
Page 114
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTD RD LATD Data Bus WR LATD or PORTD WR TRISD RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V DS39609B-page 112 Port Data ...
Page 115
... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-7: PORTD FUNCTIONS Name Bit# Buffer Type RD0/PSP0/AD0 bit 0 ST/TTL RD1/PSP1/AD1 bit 1 ST/TTL RD2/PSP2/AD2 bit 2 ST/TTL RD3/PSP3/AD3 bit 3 ST/TTL RD4/PSP4/AD4 bit 4 ST/TTL RD5/PSP5/AD5 bit 5 ST/TTL RD6/PSP6/AD6 bit 6 ST/TTL RD7/PSP7/AD7 bit 7 ST/TTL Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode ...
Page 116
... PIC18F6520/8520/6620/8620/6720/8720 10.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i ...
Page 117
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE Peripheral Out Select Peripheral Data Out RD LATE Data Bus LATE or WR PORTE CK Q Data Latch TRISE CK Q TRIS Latch RD TRISE Peripheral Enable RD PORTE Peripheral Data In Note 1: I/O pins have diode protection to V FIGURE 10-12: ...
Page 118
... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-9: PORTE FUNCTIONS Name Bit# Buffer Type RE0/RD/AD8 bit 0 ST/TTL RE1/WR/AD9 bit 1 ST/TTL RE2/CS/AD10 bit 2 ST/TTL RE3/AD11 bit 3 ST/TTL RE4/AD12 bit 4 ST/TTL RE5/AD13 bit 5 ST/TTL RE6/AD14 bit 6 ST/TTL RE7/CCP2/AD15 bit 7 ST/TTL Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode and TTL buffers when in System Bus or PSP Control mode ...
Page 119
... PIC18F6520/8520/6620/8620/6720/8720 10.6 PORTF, LATF and TRISF Registers PORTF is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i ...
Page 120
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-14: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM RD LATF Data Bus LATF or WR PORTF CK Q Data Latch TRISF CK Q Analog Input TRIS Latch Mode RD TRISF PORTF To A/D Converter or Comparator Input Note 1: I/O pins have diode protection to V DS39609B-page 118 FIGURE 10-15: ...
Page 121
... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-11: PORTF FUNCTIONS Name Bit# Buffer Type RF0/AN5 bit 0 ST RF1/AN6/C2OUT bit 1 ST RF2/AN7/C1OUT bit 2 ST RF3/AN8 bit 3 ST RF4/AN9 bit 4 ST RF5/AN10/CV bit 5 ST REF RF6/AN11 bit 6 ST RF7/SS bit 7 ST/TTL Legend Schmitt Trigger input, TTL = TTL input ...
Page 122
... PIC18F6520/8520/6620/8620/6720/8720 10.7 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corre- sponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTC pin an output (i ...
Page 123
... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-13: PORTG FUNCTIONS Name Bit# Buffer Type RG0/CCP3 bit 0 ST RG1/TX2/CK2 bit 1 ST RG2/RX2/DT2 bit 2 ST RG3/CCP4 bit 3 ST RG4/CCP5 bit 4 ST Legend Schmitt Trigger input TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 Bit 5 PORTG — ...
Page 124
... PIC18F6520/8520/6620/8620/6720/8720 10.8 PORTH, LATH and TRISH Registers Note: PORTH is available only on PIC18F8X20 devices. PORTH is an 8-bit wide, bidirectional I/O port. The cor- responding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 125
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-19: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTH RD LATD Data Bus WR LATH or PORTH WR TRISH RD TRISH External Enable System Bus Address Out Control Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-15: PORTH FUNCTIONS Name Bit# Buffer Type RH0/A16 bit 0 ST/TTL RH1/A17 bit 1 ST/TTL RH2/A18 bit 2 ST/TTL RH3/A19 bit 3 ST/TTL RH4/AN12 bit 4 ST RH5/AN13 bit 5 ST RH6/AN14 bit 6 ST RH7/AN15 bit 7 ST Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode ...
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... PIC18F6520/8520/6620/8620/6720/8720 10.9 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on PIC18F8X20 devices. PORTJ is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-21: RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTJ RD LATJ Data Bus WR LATJ or PORTJ WR TRISJ RD TRISJ Control Out System Bus External Enable Control Drive System Note 1: I/O pins have diode protection to V FIGURE 10-22: RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-17: PORTJ FUNCTIONS Name Bit# Buffer Type RJ0/ALE bit 0 ST RJ1/OE bit 1 ST RJ2/WRL bit 2 ST RJ3/WRH bit 3 ST RJ4/BA0 bit 4 ST RJ5/CE bit 5 ST RJ6/LB bit 6 ST RJ7/UB bit 7 ST Legend Schmitt Trigger input TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ ...
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... PIC18F6520/8520/6620/8620/6720/8720 10.10 Parallel Slave Port PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set asynchronously readable and writable by the external world through the RD control input pin, RE0/RD/AD8 and the WR control input pin, RE1/WR/AD9. ...
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... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 10-1: PSPCON REGISTER R-0 IBF OBF bit 7 bit 7 IBF: Input Buffer Full Status bit word has been received and is waiting to be read by the CPU word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-25: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 PORTD Port Data Latch when written; Port pins when read LATD LATD Data Output bits TRISD PORTD Data Direction bits PORTE — ...
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... PIC18F6520/8520/6620/8620/6720/8720 11.0 TIMER0 MODULE The Timer0 module has the following features: • Software selectable as an 8-bit or 16-bit timer/counter • Readable and writable • Dedicated 8-bit software programmable prescaler • Clock source selectable to be external or internal • Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode • ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE OSC 1 RA4/T0CKI pin T0SE T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE OSC 1 Programmable RA4/T0CKI Prescaler pin T0SE T0PS2, T0PS1, T0PS0 ...
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... PIC18F6520/8520/6620/8620/6720/8720 11.1 Timer0 Operation Timer0 can operate as a timer counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 regis- ter is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register ...
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... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 134 2004 Microchip Technology Inc. ...
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... PIC18F6520/8520/6620/8620/6720/8720 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module special event trigger Figure 12 simplified block diagram of the Timer1 module ...
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... PIC18F6520/8520/6620/8620/6720/8720 12.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). FIGURE 12-1: TIMER1 BLOCK DIAGRAM TMR1IF Overflow TMR1 Interrupt Flag Bit TMR1H T1OSC ...
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... PIC18F6520/8520/6620/8620/6720/8720 12.2 Timer1 Oscillator A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output enabled by setting control bit, T1OSCEN (T1CON<3>). The oscil- lator is a low-power oscillator, rated up to 200 kHz. It will continue to run during Sleep primarily intended for a 32 kHz crystal. The circuit for a typical LP oscilla- tor is shown in Figure 12-3 ...
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... PIC18F6520/8520/6620/8620/6720/8720 12.3 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 Interrupt Enable bit, TMR1IE (PIE1<0>). ...
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... PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 0x80 MOVWF TMR1H CLRF TMR1L MOVLW b’00001111’ MOVWF T1OSC CLRF secs CLRF mins MOVLW .12 MOVWF hours BSF PIE1, TMR1IE RETURN RTCisr BSF TMR1H, 7 BCF PIR1, TMR1IF INCF secs, F MOVLW ...
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... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 140 2004 Microchip Technology Inc. ...
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... PIC18F6520/8520/6620/8620/6720/8720 13.0 TIMER2 MODULE The Timer2 module timer has the following features: • 8-bit timer (TMR2 register) • 8-bit period register (PR2) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • ...
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... PIC18F6520/8520/6620/8620/6720/8720 13.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: ...
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... PIC18F6520/8520/6620/8620/6720/8720 14.0 TIMER3 MODULE The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module trigger ...
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... PIC18F6520/8520/6620/8620/6720/8720 14.1 Timer3 Operation Timer3 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). FIGURE 14-1: TIMER3 BLOCK DIAGRAM TMR3IF Overflow Interrupt Flag bit TMR3H T1OSC T1OSO/ ...
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... PIC18F6520/8520/6620/8620/6720/8720 14.2 Timer1 Oscillator The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a low- power oscillator rated up to 200 kHz. See Section 12.0 “Timer1 Module” for further details. ...
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... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 146 2004 Microchip Technology Inc. ...
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... PIC18F6520/8520/6620/8620/6720/8720 15.0 TIMER4 MODULE The Timer4 module timer has the following features: • 8-bit timer (TMR4 register) • 8-bit period register (PR4) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • ...
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... PIC18F6520/8520/6620/8620/6720/8720 15.2 Timer4 Interrupt The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 15-1: ...
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... PIC18F6520/8520/6620/8620/6720/8720 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES The PIC18FXX20 devices all have five CCP (Capture/ Compare/PWM) modules. Each module contains a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a Pulse Width Modulation (PWM) Master/Slave Duty Cycle register. Table 16-1 shows the timer resources of the CCP module modes ...
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... PIC18F6520/8520/6620/8620/6720/8720 16.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 16.1.1 ...
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... PIC18F6520/8520/6620/8620/6720/8720 16.2 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge The event is selected by control bits, CCP1M3:CCP1M0 (CCP1CON< ...
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... PIC18F6520/8520/6620/8620/6720/8720 16.3 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 register pair value or the TMR3 register pair value. When a match occurs, the CCP1 pin: • is driven High • is driven Low • toggles output (high-to-low or low-to-high) • ...
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... PIC18F6520/8520/6620/8620/6720/8720 TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 Bit 5 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN — — PIR1 PSPIF ADIF RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP PIR2 — CMIE — PIE2 — ...
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... PIC18F6520/8520/6620/8620/6720/8720 16.4 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... PIC18F6520/8520/6620/8620/6720/8720 The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 16-3: F --------------- log F PWM PWM Resolution (max) = -----------------------------bits log Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. ...
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... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 156 2004 Microchip Technology Inc. ...
Page 159
... PIC18F6520/8520/6620/8620/6720/8720 17.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 17.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE) R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit (Transmit mode only The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode new byte is received while the SSPBUF register is still holding the previous data ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.3.3 ENABLING SPI I/O To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications ...
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... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.3.8 SLEEP OPERATION In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device ...
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... PIC18F6520/8520/6620/8620/6720/8720 2 17 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
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... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I R/W-0 R/W-0 SMP CKE bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode Slew rate control disabled for standard speed mode (100 kHz and 1 MHz Slew rate control enabled for high-speed mode (400 kHz) ...
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... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I transmission to be started (must be cleared in software collision In Slave Transmit mode The SSPBUF register is written while it is still transmitting the previous word (must be ...
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... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I R/W-0 R/W-0 GCEN ACKSTAT bit 7 bit 7 GCEN: General Call Enable bit (Slave mode only Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I ation. Four mode selection bits (SSPCON<3:0>) allow 2 one of the following I C modes to be selected: 2 • Master mode, clock = (F /4) x (SSPADD + 1) ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT< ...
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... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17- SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39609B-page 172 2004 Microchip Technology Inc. ...
Page 175
... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17- SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. DS39609B-page 173 ...
Page 176
... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-10 SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39609B-page 174 2004 Microchip Technology Inc. ...
Page 177
... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-11 SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. DS39609B-page 175 ...
Page 178
... PIC18F6520/8520/6620/8620/6720/8720 17.4.4 CLOCK STRETCHING Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sam- pled low. Therefore, the CKP bit will not assert the ...
Page 180
... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-13 SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39609B-page 178 2004 Microchip Technology Inc. ...
Page 181
... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-14 SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. DS39609B-page 179 ...
Page 182
... PIC18F6520/8520/6620/8620/6720/8720 17.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.4.6 MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions ...
Page 184
... PIC18F6520/8520/6620/8620/6720/8720 2 17.4.6 Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.4.7 BAUD RATE GENERATOR Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to ‘0’ and stops until another reload has taken place ...
Page 186
... PIC18F6520/8520/6620/8620/6720/8720 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the ...
Page 187
... PIC18F6520/8520/6620/8620/6720/8720 2 17.4 MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Con- dition Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (T SDA pin is driven low ...
Page 188
... PIC18F6520/8520/6620/8620/6720/8720 2 17.4 MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sam- pled low, the Baud Rate Generator is loaded with the contents of SSPADD< ...
Page 189
... PIC18F6520/8520/6620/8620/6720/8720 2 17.4. MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next trans- mission ...
Page 190
... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-21 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39609B-page 188 2004 Microchip Technology Inc. ...
Page 191
... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-22 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. DS39609B-page 189 ...
Page 192
... PIC18F6520/8520/6620/8620/6720/8720 17.4.12 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to gen- erate an Acknowledge, then the ACKDT bit should be cleared ...
Page 193
... PIC18F6520/8520/6620/8620/6720/8720 17.4.14 SLEEP OPERATION 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
Page 194
... PIC18F6520/8520/6620/8620/6720/8720 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). b) SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored ...
Page 195
... PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF S ‘0’ ‘0’ SSPIF FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.4.17.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if low level is sampled on SDA when SCL goes from low level to high level. b) SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’. ...
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... PIC18F6520/8520/6620/8620/6720/8720 17.4.17.3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: a) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. b) After the SCL pin is deasserted, SCL is sampled low before SDA goes high ...
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... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 196 2004 Microchip Technology Inc. ...
Page 199
... PIC18F6520/8520/6620/8620/6720/8720 18.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module (also known as a Serial Communications Interface or SCI) is one of the two types of serial I/O modules available on PIC18FXX20 devices. Each device has two USARTs, which can be configured independently of each other ...
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... PIC18F6520/8520/6620/8620/6720/8720 REGISTER 18-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 CSRC bit 7 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode Master mode (clock generated internally from BRG Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit ...