PIC18F6520-I/PT Microchip Technology Inc., PIC18F6520-I/PT Datasheet - Page 130

• Manufacturer Part Number: PIC18F6520-I/PT
• Description: 64 PIN, 32 KB FLASH, 2048 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6520-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6520/8520/6620/8620/6720/8720
10.10 Parallel Slave Port
PORTD also operates as an 8-bit wide Parallel Slave
Port, or microprocessor port, when control bit
PSPMODE (PSPCON<4>) is set. It is asynchronously
readable and writable by the external world through the
RD control input pin, RE0/RD/AD8 and the WR control
input pin, RE1/WR/AD9.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD/AD8 to be the
RD input, RE1/WR/AD9 to be the WR input and RE2/
CS/AD10 to be the CS (Chip Select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set). The A/D port configuration bits,
PCFG2:PCFG0 (ADCON1<2:0>), must be set which
will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor
(PSPCON<4>) is set. In this mode, the user must make
sure that the TRISE<2:0> bits are set (pins are config-
ured as digital inputs) and the ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.
DS39609B-page 128
Note:
For PIC18F8X20 devices, the Parallel
Slave
Microcontroller mode.
port
Port
when
is
available
bit
PSPMODE
only
in
FIGURE 10-23:
One bit of PORTD
Note: I/O pin has protection diodes to V
Data Bus
Set Interrupt Flag
PSPIF (PIR1<7>)
WR LATD
or
PORTD
RD PORTD
RD LATD
TRIS Latch
Data Latch
Q
D
CK
EN
EN
Q
D
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
 2004 Microchip Technology Inc.
Chip Select
Read
Write
TTL
TTL
TTL
TTL
DD
and V
SS
RDx
pin
CS
WR
RD
.