PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 165

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.7
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Low-Power Sleep
mode before the conversion begins.
Figure 17-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are set to ‘010’ and selecting a 4 T
time before the conversion starts.
FIGURE 17-3:
FIGURE 17-4:
 2004 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO bit
1
T
Set GO bit
CY
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
T
– T
ACQT
Acquisition
Automatic
2
AD
Time
Conversion Starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
Conversion Starts
(Holding capacitor is disconnected)
AD
b8
1
3 T
AD
b9
AD
b7
2
Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared,
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
4 T
acquisition
AD
AD
AD
b8
3
b6
5 T
CYCLES (A
CYCLES (A
ADIF bit is set, holding capacitor is reconnected to analog input.
ADIF bit is set, holding capacitor is connected to analog input.
AD
b5
b7
4
6 T
AD
T
b4
5
b6
AD
7 T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
CQT
Cycles
CQT
Note:
AD
AD
b3
b5
6
<2:0> = 000, T
8
<2:0> = 010, T
wait is required before the next acquisition can
conversion
T
PIC18F1220/1320
AD
b4
b2
7
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
9 T
AD
b3
b1
8
10
ACQ
T
sample.
AD
ACQ
b0
b2
9
11
= 0)
= 4 T
10
b1
This
AD
DS39605C-page 163
)
b0
11
means
the