PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 20

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
2.7.2
The PIC18F1220/1320 devices contain circuitry to
prevent clocking “glitches” when switching between
clock sources. A short pause in the system clock
occurs during the clock switch. The length of this pause
is between 8 and 9 clock periods of the new clock
source. This ensures that the new clock source is
stable and that its pulse width will not be less than the
shortest pulse width of the two clock sources.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.
2.8
When the device executes a SLEEP instruction, the
system is switched to one of the power managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power Managed Modes” for details.
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In
SEC_IDLE), the Timer1 oscillator is operating and
providing the system clock. The Timer1 oscillator may
also run in all power managed modes if required to
clock Timer1 or Timer3.
In Internal Oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power managed mode (see Section 19.2 “Watchdog
Timer (WDT)” through Section 19.4 “Fail-Safe Clock
Monitor”). The INTOSC output at 8 MHz may be used
directly to clock the system, or may be divided down
first. The INTOSC output is disabled if the system clock
is provided directly from the INTRC output.
TABLE 2-3:
DS39605C-page 18
RC, INTIO1
RCIO, INTIO2
ECIO
EC
LP, XT and HS
Note:
Oscillator Mode
Secondary
Effects of Power Managed Modes
on the Various Clock Sources
OSCILLATOR TRANSITIONS
See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Clock
Floating, external resistor should pull high
Floating, external resistor should pull high
Floating, pulled by external clock
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
modes
(SEC_RUN
OSC1 Pin
and
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a real-
time clock. Other features may be operating that do not
require a system clock source (i.e., INTn pins, A/D
conversions and others).
2.9
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Sections 4.1 through 4.5.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 22-8) if enabled in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of 5 to 10 s following POR while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only delay that occurs when any of the EC,
RC or INTIO modes are used as the primary clock
source.
Power-up Delays
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
 2004 Microchip Technology Inc.
OSC2 Pin