PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 122
PIC16F737-I/SP
Manufacturer Part Number
PIC16F737-I/SP
Description
28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F737-ISP.pdf
(276 pages)
Specifications of PIC16F737-I/SP
A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
7K Bytes
Ram Size
192 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F7X7
10.4.7.1
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 10-18).
FIGURE 10-18:
DS30498C-page 120
Clock Arbitration
SDA
SCL
BRG
Value
BRG
Reload
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
03h
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place and BRG starts its count
01h
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
DX – 1
SCL allowed to transition high
03h
2004 Microchip Technology Inc.
02h
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