PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 144

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
11.2.3
When setting up an Asynchronous Reception with
Address Detect enabled:
• Initialize the SPBRG register for the appropriate
• Enable the asynchronous serial port by clearing
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 11-6:
DS30498C-page 142
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
bit SYNC and setting bit SPEN.
F
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
RC7/RX/DT
OSC
Baud Rate Generator
AUSART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
and Control
Pin Buffer
RSR<8>
SPEN
ADDEN
ADDEN
RX9
RX9
Recovery
Interrupt
Data
or
64
16
CREN
Enable
Load of
Receive
Buffer
• Flag bit RCIF will be set when reception is
• Read the RCSTA register to get the ninth bit and
• Read the 8-bit received data by reading the
• If any error occurred, clear the error by clearing
• If the device has been addressed, clear the
RCIF
RCIE
complete and an interrupt will be generated if
enable bit RCIE was set.
determine if any error occurred during reception.
RCREG register to determine if the device is
being addressed.
enable bit CREN.
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer and interrupt the
CPU.
RX9
MSb
Stop
RX9D
(8)
OERR
7
RSR Register
RCREG Register
8
 2004 Microchip Technology Inc.
Data Bus
8
8
1
FERR
0
Start
LSb
FIFO