PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 44

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
4.7.2
The core and peripherals can be configured to be
clocked by T1OSC using a 32.768 kHz crystal. The
crystal must be connected to the T1OSO and T1OSI
pins. This is the same configuration as the low-power
timer circuit (see Section 7.6 “Timer1 Oscillator”).
When SCS bits are configured to run from T1OSC, a
clock transition is generated. It will clear the OSTS bit,
switch the system clock from either the primary system
clock or INTRC, depending on the value of SCS<1:0>
and FOSC<2:0>, to the external low-power Timer1
oscillator input (T1OSC) and shut-down the primary
system clock to conserve power.
After a clock switch has been executed, the internal Q
clocks are held in the Q1 state until eight falling edge
clocks are counted on the T1OSC. After the eight clock
periods have transpired, the clock input to the Q clocks
is released and operation resumes (see Figure 4-8). In
addition, T1RUN (in T1CON) is set to indicate that
T1OSC is being used as the system clock.
FIGURE 4-8:
DS30498C-page 42
SCS<1:0>
Note 1:
Program
Counter
System
T1OSI
OSC1
Clock
2:
3:
4:
T
T
T
T
OSC
SCS
T
DLY
Q1
SEC_RUN MODE
1
T
P
OSC (2)
= 8 T
= 1 T
Q2
= 30.52 s.
= 50 ns minimum.
PC
Q3
T
T
1
1
P
P
.
Q4
TIMING DIAGRAM FOR SWITCHING TO SEC_RUN MODE
Q1
T
DLY
(4)
T
T
1
P
(1)
T
SCS (3)
PC + 1
Note 1: The T1OSCEN bit must be enabled and it
Q1
2: When T1OSCEN = 0, the following
Q2
A clock switching event will occur if the
final state of the SCS bits is different from
the original.
is the user’s responsibility to ensure
T1OSC is stable before clock switching to
the T1OSC input clock can occur.
possible effects result.
SCS<1:0>
Original
00
00
10
10
Q3
Q4
 2004 Microchip Technology Inc.
SCS<1:0>
Modified
Q1
01
11
11
01
Q2
PC + 2
00 – no change
10 – INTRC
10 – no change
00 – Oscillator
defined by
FOSC<2:0>
Q3
SCS<1:0>
Final
Q4
PC + 3
Q1