PIC16F1933-I/SO Microchip Technology Inc., PIC16F1933-I/SO Datasheet - Page 110

• Manufacturer Part Number: PIC16F1933-I/SO
• Description: 28 SOIC .300in TUBE, 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1933-I/SO

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16F193X/LF193X
9.1.1
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
FIGURE 9-1:
TABLE 9-1:
DS41364D-page 110
Name
INTCON
IOCBF
IOCBN
IOCBP
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
STATUS
WDTCON
Legend:
Instruction Flow
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
(INTCON reg.)
Note
Interrupt flag
GIE bit
Instruction
Fetched
Instruction
Executed
CLKOUT
cleared.
OSC1
1:
2:
3:
4:
PC
(1)
(2)
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.
WAKE-UP USING INTERRUPTS
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
T
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TMR1GIE
TMR1GIF
OST
IOCBN7
IOCBP7
IOCBF7
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
OSFIE
OSFIF
Bit 7
GIE
—
—
—
—
Inst(PC - 1)
= 1024 T
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
IOCBF6
IOCBN6
IOCBP6
CCP5IE
CCP5IF
PEIE
ADIE
ADIF
Bit 6
C2IE
C2IF
(drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
—
—
Inst(PC + 1)
Sleep
PC + 1
TMR0IE
IOCBN5
IOCBP5
IOCBF5
CCP4IE
CCP4IF
RCIE
RCIF
Bit 5
C1IE
C1IF
—
Processor in
Sleep
IOCBN4
IOCBF4
IOCBP4
CCP3IE
CCP3IF
PC + 2
INTE
TXIE
EEIE
TXIF
EEIF
Bit 4
TO
Preliminary
T
OST (3)
WDTPS<4:0>
IOCBF3
IOCBN3
IOCBP3
TMR6IE
TMR6IF
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPIE
BCLIE
SSPIF
BCLIF
IOCIE
Bit 3
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
PD
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
PC + 2
tion of a SLEEP instruction
- SLEEP instruction will be completely exe-
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
cuted
IOCBN2
IOCBP2
CCP1IE
TMR0IF
IOCBF2
CCP1IF
LCDIE
LCDIF
Bit 2
—
—
Z
(4)
Dummy Cycle
PC + 2
IOCBN1
TMR2IE
IOCBF1
IOCBP1
TMR4IE
TMR2IF
TMR4IF
Bit 1
INTF
DC
—
—
 2009 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
0004h
SWDTEN
IOCBF0
IOCBN0
IOCBP0
TMR1IE
CCP2IE
TMR1IF
CCP2IF
IOCIF
Bit 0
—
—
C
Inst(0005h)
Inst(0004h)
Register on
0005h
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