PIC16F1933-I/SO Microchip Technology Inc., PIC16F1933-I/SO Datasheet - Page 43

• Manufacturer Part Number: PIC16F1933-I/SO
• Description: 28 SOIC .300in TUBE, 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1933-I/SO

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 3-14:
 2009 Microchip Technology Inc.
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
Legend:
Note
Address
Bank 2
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(1, 2)
(2)
1:
2:
3:
4:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATB
LATC
LATD
LATE
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
APFCON
—
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are trans-
ferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
The Capacitive Sensing Reference Mode (CPSRM) bit is not available for the PIC16F/LF1934/1936/1937 devices.
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
PORTA Data Latch
PORTB Data Latch
PORTC Data Latch
PORTD Data Latch
Unimplemented
Unimplemented
Unimplemented
SBOREN
C1INTP
C2INTP
DACEN
SRSPE
FVREN
SRLEN
C1ON
C2ON
Bit 7
GIE
—
—
—
—
—
---
—
Write Buffer for the upper 7 bits of the Program Counter
CCP3SEL
FVRRDY
SRSCKE
DACLPS
SRCLK2
C1INTN
C2INTN
C1OUT
C2OUT
PEIE
Bit 6
—
—
—
—
—
---
Reserved
SRSC2E
C1PCH1
C2PCH1
SRCLK1
T1GSEL
TMR0IE
DACOE
C1OE
C2OE
Bit 5
—
—
—
—
—
---
Preliminary
Reserved
C1PCH0
C2PCH0
SRCLK0
SRSC1E
P2BSEL
C1POL
C2POL
Bit 4
INTE
TO
—
—
—
---
SRNQSEL C2OUTSEL
CDAFVR1
SRQEN
SRRPE
LATE3
IOCIE
PIC16F193X/LF193X
Bit 3
PD
DACPSS<1:0>
—
—
—
—
—
—
DACR<4:0>
BSR<4:0>
CDAFVR0
SRNQEN
SRRCKE
LATE2
TMR0IF
C1SP
C2SP
Bit 2
—
—
—
—
Z
(3)
MC2OUT MC1OUT ---- --00 ---- --00
LATE1
SRRC2E
C1HYS
C2HYS
SSSEL
SRPS
INTF
Bit 1
DC
—
---
C1NCH<1:0>
C2NCH<1:0>
ADFVR<1:0>
(3)
CCP2SEL -000 0000 -000 0000
BORRDY 1--- ---q u--- ---u
C1SYNC 0000 -100 0000 -100
C2SYNC 0000 -100 0000 -100
DACNSS 000- 00-0 000- 00-0
SRRC1E 0000 0000 0000 0000
LATE0
IOCIF
SRPR
Bit 0
C
(3)
DS41364D-page 43
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 --00 0000 --00
0000 --00 0000 --00
0q00 0000 0q00 0000
---0 0000 ---0 0000
0000 0000 0000 0000
POR, BOR
Value on:
—
—
—
Value on all
Resets
other
—
—
—