PIC16F1933-I/SO Microchip Technology Inc., PIC16F1933-I/SO Datasheet - Page 64

• Manufacturer Part Number: PIC16F1933-I/SO
• Description: 28 SOIC .300in TUBE, 7KB Flash, 256B RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1933-I/SO

• A/d Inputs: 11-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16F193X/LF193X
REGISTER 4-1:
DS41364D-page 64
bit 13
bit 6
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4-3
Note 1:
FCMEN
R/P-1/1
R/P-1/1
MCLRE
2:
3:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire data EEPROM will be erased when the code protection is turned off during an erase.
The entire program memory will be erased when the code protection is turned off.
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT
0 = CLKOUT function is enabled on RA6/CLKOUT
BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
CPD: Data Code Protection bit
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: RE3/MCLR/V
If LVP bit = 1:
If LVP bit = 0:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
This bit is ignored.
1 = RE3/MCLR/V
0 = RE3/MCLR/V
PWRTE
R/P-1/1
R/P-1/1
CONFIGURATION WORD 1
IESO
bit..
W = Writable bit
‘0’ = Bit is cleared
x = Bit is unknown
CLKOUTEN
PP
PP
PP
R/P-1/1
R/P-1/1
WDTE1
(3)
pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3
pin function is MCLR; Weak pull-up enabled.
Pin Function Select bit
(2)
(1)
Preliminary
BOREN1
WDTE0
R/P-1/1
R/P-1/1
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
P = Programmable bit
BOREN0
R/P-1/1
R/P-1/1
FOSC2
 2009 Microchip Technology Inc.
R/P-1/1
R/P-1/1
FOSC1
CPD
R/P-1/1
R/P-1/1
FOSC0
CP
bit 7
bit 0