PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 121

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.4
The ADCON1, ANSEL, TRISA and TRISB registers
control the operation of the A/D port pins. The port pins
that are desired as analog inputs must have their
corresponding TRIS bits set (input). If the TRIS bit is
cleared (output), the digital output level (V
will be converted.
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
FIGURE 12-3:
FIGURE 12-4:
 2005 Microchip Technology Inc.
Note 1: When reading the Port register, all pins
2: Analog levels on any pin that is defined as
Configuring Analog Port Pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
a digital input (including the RA4:RA0 and
RB7:RB6 pins), may cause the input
buffer to consume current out of the
device specification.
T
CY
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
7
to T
0000 00
ADRESH
AD
Conversion starts
A/D CONVERSION T
A/D RESULT JUSTIFICATION
T
AD
1
2 1 0 7
ADFM = 1
T
AD
b9
Right Justified
2
10-bit Result
T
ADRESL
AD
b8
3
OH
T
AD
b7
AD
or V
4
0
CYCLES
T
OL
AD
b6
10-bit Result
5
)
T
AD
b5
6
12.5
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2 T
acquisition is started. After this 2 T
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
In Figure 12-3, after the GO/DONE bit is set, the first
time segment has a minimum of T
T
12.5.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 12-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
ADRES is loaded,
GO/DONE bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input
T
AD
AD
b4
Note:
.
7
7
T
AD
b3
ADRESH
A/D Conversions
10-bit Result
Left Justified
8
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
A/D RESULT REGISTERS
T
AD
b2
ADFM = 0
9
AD
T
0 7 6 5
AD
wait is required before the next
PIC16F87/88
b1
10 T
ADRESL
AD
b0
0000 00
11
CY
AD
DS30487C-page 119
and a maximum of
0
wait, acquisition