PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 222

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
S
SCI. See AUSART.
SCL .................................................................................... 93
Serial Communication Interface. See AUSART.
Slave Mode
Sleep ................................................................ 129, 132, 145
Software Simulator (MPLAB SIM) .................................... 158
Software Simulator (MPLAB SIM30) ................................ 158
SPBRG Register ................................................................ 15
Special Event Trigger ....................................................... 120
Special Features of the CPU ............................................ 129
Special Function Registers ................................................ 14
Special Function Registers (SFRs) .................................... 14
SPI
SSP
SSPADD Register .............................................................. 15
SSPBUF Register .............................................................. 14
SSPCON Register .............................................................. 14
SSPOV ............................................................................... 89
SSPOV Bit .......................................................................... 93
SSPSTAT Register ............................................................ 15
Stack .................................................................................. 25
STATUS Register
Synchronous Master Reception
Synchronous Master Transmission
Synchronous Serial Port (SSP) .......................................... 87
Synchronous Slave Reception
Synchronous Slave Transmission
T
T1CKPS0 Bit ...................................................................... 72
T1CKPS1 Bit ...................................................................... 72
T1CON Register ................................................................. 14
T1OSCEN Bit ..................................................................... 72
T1SYNC Bit ........................................................................ 72
T2CKPS0 Bit ...................................................................... 80
T2CKPS1 Bit ...................................................................... 80
T2CON Register ................................................................. 14
T
Time-out Sequence .......................................................... 134
DS30487C-page 220
AD
................................................................................... 118
SCL ............................................................................ 93
SDA ............................................................................ 93
Associated Registers ................................................. 90
Serial Clock ................................................................ 87
Serial Data In ............................................................. 87
Serial Data Out .......................................................... 87
Slave Select ............................................................... 87
ACK ............................................................................ 93
I
Overflows ................................................................... 25
Underflow ................................................................... 25
C Bit ........................................................................... 17
DC Bit ......................................................................... 17
IRP Bit ........................................................................ 17
PD Bit ................................................................. 17, 132
RP Bits ....................................................................... 17
TO Bit ................................................................. 17, 132
Z Bit ............................................................................ 17
Associated Registers ............................................... 110
Associated Registers ............................................... 109
Overview .................................................................... 87
SPI Mode ................................................................... 87
Associated Registers ............................................... 112
Associated Registers ............................................... 111
2
C
I
2
C Operation ..................................................... 92
Timer0 ................................................................................ 67
Timer1 ................................................................................ 71
Timer2 ................................................................................ 79
Timing Diagrams
Associated Registers ................................................. 69
Clock Source Edge Select (T0SE Bit) ....................... 18
Clock Source Select (T0CS Bit) ................................. 18
External Clock ............................................................ 68
Interrupt ..................................................................... 67
Operation ................................................................... 67
Overflow Enable (TMR0IE Bit) ................................... 19
Overflow Flag (TMR0IF Bit) ..................................... 140
Overflow Interrupt .................................................... 140
Prescaler ................................................................... 68
T0CKI ........................................................................ 68
Associated Registers ................................................. 77
Capacitor Selection .................................................... 75
Counter Operation ..................................................... 73
Operation ................................................................... 71
Operation in Asynchronous Counter Mode ................ 74
Operation in Synchronized Counter Mode ................. 73
Operation in Timer Mode ........................................... 73
Oscillator .................................................................... 75
Oscillator Layout Considerations ............................... 75
Prescaler ................................................................... 76
Resetting Timer1 Register Pair .................................. 76
Resetting Timer1 Using a CCP Trigger Output ......... 76
Use as a Real-Time Clock ......................................... 76
Associated Registers ................................................. 80
Output ........................................................................ 79
Postscaler .................................................................. 79
Prescaler ................................................................... 79
Prescaler and Postscaler ........................................... 79
A/D Conversion ........................................................ 191
Asynchronous Master Transmission ........................ 103
Asynchronous Master Transmission
Asynchronous Reception ......................................... 104
Asynchronous Reception with
Asynchronous Reception with
AUSART Synchronous Receive
AUSART Synchronous Transmission
Brown-out Reset ...................................................... 181
Capture/Compare/PWM (CCP1) ............................. 183
CLKO and I/O .......................................................... 180
External Clock .......................................................... 179
Fail-Safe Clock Monitor ........................................... 144
I
I
I
I
Primary System Clock After Reset
Primary System Clock After Reset
PWM Output .............................................................. 84
Reset, Watchdog Timer, Oscillator Start-up
Slow Rise Time (MCLR Tied to V
2
2
2
2
C Bus Data ............................................................ 187
C Bus Start/Stop Bits ............................................ 186
C Reception (7-Bit Address) ................................... 94
C Transmission (7-Bit Address) .............................. 94
Reading and Writing .......................................... 74
(Back to Back) ................................................. 103
Address Byte First ........................................... 107
Address Detect ................................................ 107
(Master/Slave) ................................................. 189
(Master/Slave) ................................................. 189
(EC, RC, INTRC) ............................................... 48
(HS, XT, LP) ...................................................... 47
Timer and Power-up Timer .............................. 181
Through RC Network) ...................................... 138
 2005 Microchip Technology Inc.
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